The M24M01-R, M24M01-HR and M24M01-W are I²C-compatible electrically erasable programmable memory (EEPROM) devices organized as 128 Kb × 8 bits.
The I²C bus is a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I²C bus inition.
The M24M01-R, M24M01-HR and M24M01-W behave as slaves in the I²C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are generated by the bus master and initiated by a Start condition, followed by the device select code, address bytes and data bytes. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way
Generic Part Number | Storage Capacity | Serial Interface | Marketing Status | Supply Voltage(Vcc) | Supply Voltage(Vcc) | Clock Frequency(fSCL) | Package |
spec | min | max | max | ||||
kB | V | V | MHz | ||||
M24M01-HR | 1000 | I²C | Active | 1.8 | 5.5 | 1 | SO8 |
M24M01-R | 1000 | I²C | Active | 1.8 | 5.5 | 1 | SO 08 WIDE .208 (EIAJ); SO8; UNSAWN WAFER V.I. 100% |
M24M01-W | 1000 | I²C | Preview | 1.8 | 5.5 | 0.4 | SO8 |
M95M01-R | 1000 | SPI | Active | 1.8 | 5.5 | 5 | SO 08 WIDE .208 (EIAJ); SO8 |