M34D64-W 128K,64K串行I²C总线的EEPROM
The M34D64-W are I²C-compatible electrically erasable programmable memory (EEPROM) devices organized as 8192 x 8 bits.
These devices are compatible with the I²C memory protocol. This is a two-wire serial interface that uses a bidirectional databus and serial clock. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I²C bus inition.
The device behaves as a slave in the I²C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and Read/Write bit (RW) (as described in Table 2.: Device select code), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
M34D64-W 订购型号:
| Ordering Model | Storage Capacity | Serial Interface | Marketing Status | Supply Voltage(Vcc) | Supply Voltage(Vcc) | Clock Frequency(fSCL) | Package | ESample Flag |
| spec | min | max | max | |||||
| kB | V | V | MHz | |||||
| M34D64-WMN6P | 64 | I²C | Active | 2.5 | 5.5 | 0.4 | SO8 | No |
| M34D64-WMN6TP | 64 | I²C | Active | 2.5 | 5.5 | 0.4 | SO8 | No |
M34D64-W 特性:
- Two-wire I²C serial interface supports 400 kHz protocol
- Single supply voltage:
– 2.5 to 5.5 V for M34D64-W - Hardware write control of the top quarter of memory
- byte and page write (up to 32 bytes)
- Random and Sequential Read modes
- Self-timed programming cycle
- Automatic address incrementing
- Enhanced ESD/latch-up protection
- More than 1 000 000 Write cycles
- More than 40-year data retention
- Packages
– ECOPACK? (RoHS compliant)
M34D64-W 技术支持与电子电路设计开发资源下载
- M34D64-W 数据手册DataSheet下载.PDF
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