ADS5413-11 11 位 65MSPS ADC，具有单通道、高 IF 和高带宽
|
ADS5413-11 |
| Resolution(Bits) |
11 |
| Sample Rate (max) |
65MSPS |
| Architecture |
Pipeline |
| Power Consumption(Typ)(mW) |
400 |
| SINAD(dB) |
65 |
| SNR(dB) |
65 |
| SFDR(dB) |
77 |
| DNL(Max)(+/-LSB) |
0.75 |
| INL(Max)(+/-LSB) |
1 |
| No Missing Codes(Bits) |
11 |
| ENOB(Bits) |
10.5 |
| No. of Supplies |
2 |
| Analog Voltage AV/DD(Min)(V) |
3.0 |
| Analog Voltage AV/DD(Max)(V) |
3.6 |
| Logic Voltage DV/DD(Min)(V) |
1.6 |
| Logic Voltage DV/DD(Max)(V) |
2.0 |
| Input Configuration Range |
2V (p-p) |
| Reference Mode |
Int and Ext |
| Rating |
Catalog |
| Pin/Package |
48HTQFP |
| # Input Channels |
1 |
| Operating Temperature Range(°C) |
-40 to 85 |
ADS5413-11 说明
The ADS5413-11 is a low power, 11-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from a single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous sampling. The device can also be clocked with single ended or differential clock, without change in performance. The internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the application.
ADS5413-11 特性
- 11-Bit Resolution
- 65-MSPS Maximum Sample Rate
- 2-Vpp Differential Input Range
- 3.3-V Single Supply Operation
- 1.8-V to 3.3-V Output Supply
- 400-mW Total Power Dissipation
- Two’s Complement Output Format
- On-Chip S/H and Duty Cycle Adjust Circuit
- Internal or External Reference
- 63.3-dBFS SNR and 72.9-dBc SFDR at 65 MSPS and 220-MHz Input
- Power-Down Mode
- Single-Ended or Differential Clock
- 1-GHz –3-dB Input Bandwidth
- 48-Pin TQFP Package With PowerPad (7 mm x 7 mm body size)
- APPLICATIONS
- Cellular Base Transceiver Station Receive Channel
- High IF Sampling Applications
- CDMA: IS-95, UMTS, CDMA1X
- TDMA: GSM, IS-136, EDGE/UWC-136
- Wireless Local Loop
ADS5413-11 芯片订购指南
| 器件 |
状态 |
温度 (oC) |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| ADS5413-11IPHP |
ACTIVE |
-40 to 85 |
18.45 | 1ku |
HTQFP (PHP) | 48 |
250 | JEDEC TRAY (10+1) |
|
| ADS5413-11IPHPG4 |
ACTIVE |
-40 to 85 |
18.45 | 1ku |
HTQFP (PHP) | 48 |
250 | JEDEC TRAY (10+1) |
|
ADS5413-11 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| ADS5413-11IPHP |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
|
ADS5413-11IPHP |
| ADS5413-11IPHPG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
|
ADS5413-11IPHPG4 |
ADS5413-11 应用技术支持与电子电路设计开发资源下载
- ADS5413-11 数据资料 dataSheet 下载.PDF
- TI 德州仪器仪ADC 模数转换器产品选型与价格 . xls
- 模数规格和性能特性术语表 (Rev. A) (PDF 1993 KB)
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 高速数据转换 (PDF 1967 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF
1305 KB)
- A
Spreadsheet for Calculating the Frequency Response of the ADS1250-54 (PDF
461 KB)
- A Spreadsheet for Calculating the Frequency Response of the
ADS1250-54
- Understanding the ADS1251, ADS1253, and ADS1254 Input
Circuitry (PDF 39 KB)
- Analog-to-Digital Converter Grounding Practices Affect System
Performance (PDF 56 KB)
- Principles of Data Acquisition and Conversion (PDF 50 KB)
- Interleaving Analog-to-Digital Converters (PDF 64 KB)
- What
Designers Should Know About Data Converter Drift (PDF 95 KB)
- Giving Delta-Sigma Converters a Gain Boost with a Front End
Analog Gain Stage (PDF 70 KB)
- Programming Tricks for Higher Conversion Speeds Utilizing Delta
Sigma Converters (PDF 105 KB)
ADS5413-11 工具与软件
