| Key | Value |
|---|---|
| F.max (MHz): | 100 MHz |
| Max. Operating Freq. (MHz): | 100 MHz |
| Max I/O Pins: | 384 |
| Speed: | -2 |
| Registers: | 2304 |
| Usable Gates: | 40K - 50K |
| Memory: | 18432 |
This 40,000 to 50,000-gate coprocessor is a fully PCI-compliant, SRAM-based FPGA with distributed 10-ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic® ability (partially or fully reconfigurable without loss of data), and automatic component generators. It has a 384 I/O count and supports a 5-V design. It can be used as a coprocessor for high-speed (DSP/processor-based) designs by implementing a variety of computation intensive, arithmetic functions. It is designed to quickly implement high-performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC or Sun platform.
