Doc ID: DOC-1448
Change
The bit descriptions are missing for the M4P_CACHE_PEADDR.REPSET, M4P_CACHE_PEADDR.PESET, and M4P_CACHE_PEADDR.PEBNK bits. The descriptions are as follows:
M4P_CACHE_PEADDR.REPSET - Cache Set of State Machine Memory Error
M4P_CACHE_PEADDR.PESET - Cache Set of Bank Parity Error.
M4P_CACHE_PEADDR.PEBNK - Cache Bank of Parity Error.
Doc ID: DOC-1513
Change
The description of the M4P_SRAM_CFG.CDBANKS field in table 2-16 (M4P_SRAM_CFG Register Fields) should change to:
M4P_SRAM_CFG Register Fields Bit No.
(Access)
Bit Name
Description/Enumeration
3:0
(R/W)
CDBANKS
Code/Data Banks Partition.
The
M4P_SRAM_CFG.CDBANKSfield controls the partitioning of main SRAM resources between the code address range and the SRAM (data) address range . TheM4P_SRAM_CFG.CDBANKSfield indicates how many of the 64K byte config banks of SRAM are allocated to the code region; the remaining available banks are allocated to the SRAM (data) region.When the
M4P_SRAM_CFG.CDBANKSfield is changed, the contents of any banks which are deducted from a given region are lost. The contents of any banks which are added to a given region are undefined, but should be zeroed immediately for security purposes.0
0 code banks, 6 data banks
1
1 code bank, 5 data banks
2
2 code banks, 4 data Banks
3
3 code banks, 3 data banks
3
4 code banks, 2 data banks
3
5 code banks, 1 data bank
3
6 code banks, 0 data banks
Doc ID: DOC-1449
Change
The bit descriptions are missing for the M4P_BUSFLT.ADDR and M4P_BUSFLT.STAT bits. The bit descriptions are as follows:
M4P_BUSFLT.ADDR - Bus Fault Address. This configuration option is not available, so the ADDR field of the BUSFLT register always reads zero.
M4P_BUSFLT.STAT - Bus Fault Status. This bit drives M4P_BUSFLT interrupt, and is set on the detection of a posted write bus fault. This bit is cleared if written with a 1.
Doc ID: DOC-1450
Change
The register and bit descriptions are missing for the CGU_TSVALUE0, CGU_TSVALUE1, CGU_TSCOUNT0, and CGU_TSCOUNT1 registers/bits. The register/bit descriptions are as follows:
CGU_TSVALUE0 - The CGU_TSVALUE0 register holds the least significant bits (bits [31:0]) value that is initially loaded to the CoreSight timestamp counter.
CGU_TSVALUE1 - The CGU_TSVALUE1 register holds the least significant bits (bits [31:0]) value that is initially loaded to the CoreSight timestamp counter.
CGU_TSCOUNT0 - The CGU_TSCOUNT0 register address is used to read the CoreSight Timestamp counter LSB 32-bit (bits [31:0]) value.
CGU_TSCOUNT1 - The CGU_TSCOUNT1 register address is used to read the CoreSight Timestamp counter LSB 32-bit (bits [31:0]) value.
Doc ID: DOC-1451
Change
In the Autobaud detection section, the process of using the width capture (WIDCAP) mode for UART autobaud detection is described, but the actual (processor specific) timer-to-counter mapping is not identified on page 13-9 in the description of WIDCAP. The mapping is as follows:
TACI5 is routed to UART0 Rx
TACI2 is routed to UART1 Rx
TACI3 is routed to UART2 Rx
Doc ID: DOC-1447
Change
The ADSP-CM40x does not support boot forwarding. The following references to this feature should be removed:
Page 29-1: delete ", forwarding data to a peripheral,"
Page 29-4 in table 29-1: delete "BFLAG_FORWARD Forward payload to a device. Must be used in conjunction with the BFLAG_INDIRECT flag." (Bit 7 is reserved.)
Page 29-10: delete "FORWARD ,"
Doc ID: DOC-1445
Change
In figure 29-6 (SPI Memory Connections) the Ohm symbol is not clear (two places).
Doc ID: DOC-1446
Change
In figure 29-9 (Connection Between Host--SPI Master--and Processor--SPI Slave), figure 29-10 (Connection Between Host--SPI Master--and Processor--SPI Slave--DIOM), and figure 29-11 (Connection Between Host--SPI Master--and Processor--SPI Slave--QSPI), the pull-up resistor value is omitted (TBD). The value should be shown as 10K Ohms.
Doc ID: DOC-1459
Change
The following registers are available and will be added to the next manual revision.
Analog Devices Identification Register (ADIID, Address 0x40002020) The ADIID identification register is a 16-bit field that is present on all implementations of the Cortex low power platform. It is designed to be used by debuggers to confirm that the device that they are connected to via a serial wire is an implementation of the Cortex low power platform from Analog Devices. Debuggers can subsequently check the CHIPID identification register to which particular implementation it actually is. The value of 0x4144 is contained in this register. This value does not vary between implementations. This register is located at 0x40002020. This address and value have been notified to tool vendors for device identification purposes.
Bits [15:0] of this register have a fixed value of 0x4144.
Chip ID (Address 0x40002024) The CHIPID identification register is a 16-bit field that is unique to an implementation of this Cortex low power platform. It can be used by code running on the Cortex to tailor its operation for that implementation. It is also designed for use by the serial wire debug tools to allow external debuggers to check the particular implementation of the Cortex low power platform and to tailor its operation for that implementation. This register is located at 0x40002024.
Bits [15:4]- Part Identifier
Bits [3:0] – Silicon Revision number (Default value zero)
Doc ID: DOC-1471
Change
The SPI Flash chapter is not present in the ADSP-CM40x Mixed-Signal Control Processor Hardware Reference (rev. 0.2). This chapter is available at the following URL:
Last Update Date: 2014-03-04
