TriCore®架构 & 内核

1999年，英飞凌发布了第一代AUDO（汽车统一处理器）。这颗32位TriCore™单片机基于统一的RISC/MCU/DSP处理器内核，拥有强大的计算能力。从那时起，英 飞凌就不断改进和优化这个产品家族，几经演进，便有了如今的第四代TriCore™。最新推出的AUDO MAX家族（版本1.6）立足于TriCore™架构，设立了高端市场的性能新标准。& #160;

Product Brief
TitleSizeDateVersion
TriCore™ Product Brief-IPextreme135 KB07 二月 201101_00
TriCore™ Product Brief-IPextreme135 KB07 二月 201101_00
User Manual
TitleSizeDateVersion
TriLib DSP Library User's Manual4.3 MB06 八月 200701_02
TriCore™ 1 Architecture Overview Handbook1.1 MB07 二月 2011
TriCore™ DSP Optimization Guide Part 2: Routines3.3 MB07 二月 2011
TriCore™ 1 DSP Optimization Guide Part 1: Instruction Set7.7 MB07 二月 2011
TriCore™ 1 DSP Optimization Guide Part 1: Instruction Set7.7 MB07 二月 2011
TriCore™ 1 DSP Optimization Guide Part 1: Examples320 KB07 二月 201101_01
TriCore™ 1 DSP Optimization Guide Part 2: Routines3.3 MB07 二月 2011
TriCore™ 1 DSP Optimization Guide Part 2: Examples290 KB07 二月 201101_01
TriCore™ 1 Architecture Volume 1: Core Architecture V1.3 & V1.3.12.4 MB03 一月 2012
TriCore™ 1 Architecture Volume 2: Instruction Set V1.3 & V1.3.18.6 MB03 一月 2012
Addendum for TriCore™ Architecture Manual, Vol2, V1.3.8, pages493/494225 KB23 十一月 2009
TriCore™ 1 Architecture Overview Handbook1.1 MB07 二月 2011
TriLib DSP Library User's Manual4.3 MB06 八月 200701_02
TriCore™ Compiler Writer's Guide1.5 MB07 二月 201101_04
TriCore™ EABI User's Manual714 KB07 二月 201102_03
TriCore™ Architecture Volume 1: Core Architecture V1.67 MB11 五月 201201_00
TriCore™ Architecture Volume 2: Instruction Set V1.610.6 MB14 五月 201201_00
Application Notes
TitleSizeDateVersion
AP24026 - EMC and System-ESD Design Guidelines for Board Layout；EN2.9 MB15 三月 201603_05
TC1782 Electric motor control - software315 KB16 九月 201101_00
Concurrent multi-threaded execution - description1.2 MB30 四月 201001_00
TriCore™ 1 DSP Kernel Benchmarks (AP32073)456 KB07 二月 201101_00
Memory Access Time in TC1M based systems195 KB03 八月 200701_01
Memory Access Time in TC1M based systems (AP32065)316 KB07 八月 200701_01
Concurrent multi-threaded execution - software466 KB04 十月 201001_00
Interrupt Response Time in TC1M Based Systems(AP32076)263 KB03 八月 200701_00
TriCore™ 1 Pipeline Behaviour & Instruction Execution Timing (AP32071)431 KB07 二月 201101_00
TC1M Synchronization Primitives (AP32066)228 KB03 八月 200701_01
TC1M Cache Management (AP32067)348 KB06 八月 200701_01
TC1M Synchronization Primitives (AP32066)331 KB07 八月 200701_01
Interrupt Response Time in TC1M based Systems (AP32076)263 KB07 八月 200701_00
TriCore™ DSP Kernel Benchmarks (AP32073)642 KB07 二月 201101_00
TriCore™ Pipeline Behaviour & Instruction Execution Timing (AP32071)1.1 MB07 二月 201101_00
Presentations
TitleSizeDateVersion
Introduction Presentation1.7 MB11 十月 201201_00
Introduction955 KB11 十月 201201_00
TriCore™ Product Brief-IPextreme tricore-tm-architecture-and-core
TriCore™ Product Brief-IPextreme tricore-tm-architecture-and-core
TriLib DSP Library User's Manual tricore-tm-architecture-and-core
TriCore™ 1 Architecture Overview Handbook tricore-tm-architecture-and-core
TriCore™ DSP Optimization Guide Part 2: Routines tricore-tm-architecture-and-core
TriCore™ 1 DSP Optimization Guide Part 1: Instruction Set tricore-tm-architecture-and-core
TriCore™ 1 DSP Optimization Guide Part 1: Instruction Set tricore-tm-architecture-and-core
TriCore™ 1 DSP Optimization Guide Part 1: Examples tricore-tm-architecture-and-core
TriCore™ 1 DSP Optimization Guide Part 2: Routines tricore-tm-architecture-and-core
TriCore™ 1 DSP Optimization Guide Part 2: Examples tricore-tm-architecture-and-core
TriCore™ 1 Architecture Volume 1: Core Architecture V1.3 & V1.3.1 tricore-tm-architecture-and-core
TriCore™ 1 Architecture Volume 2: Instruction Set V1.3 & V1.3.1 tricore-tm-architecture-and-core
Addendum for TriCore™ Architecture Manual, Vol2, V1.3.8, pages493/494 tricore-tm-architecture-and-core
TriCore™ 1 Architecture Overview Handbook tricore-tm-architecture-and-core
TriLib DSP Library User's Manual tricore-tm-architecture-and-core
TriCore™ Compiler Writer's Guide tricore-tm-architecture-and-core
TriCore™ EABI User's Manual tricore-tm-architecture-and-core
TriCore™ Architecture Volume 1: Core Architecture V1.6 tricore-tm-architecture-and-core
TriCore™ Architecture Volume 2: Instruction Set V1.6 tricore-tm-architecture-and-core
EN SAK-C505CA-2RM+CA
TC1782 Electric motor control - software tricore-tm-architecture-and-core
Concurrent multi-threaded execution - description tricore-tm-architecture-and-core
TriCore™ 1 DSP Kernel Benchmarks (AP32073) tricore-tm-architecture-and-core
Memory Access Time in TC1M based systems tricore-tm-architecture-and-core
Memory Access Time in TC1M based systems (AP32065) tricore-tm-architecture-and-core
Concurrent multi-threaded execution - software tricore-tm-architecture-and-core
Interrupt Response Time in TC1M Based Systems(AP32076) tricore-tm-architecture-and-core
TriCore™ 1 Pipeline Behaviour & Instruction Execution Timing (AP32071) tricore-tm-architecture-and-core
TC1M Synchronization Primitives (AP32066) tricore-tm-architecture-and-core
TC1M Cache Management (AP32067) tricore-tm-architecture-and-core
TC1M Synchronization Primitives (AP32066) tricore-tm-architecture-and-core
Interrupt Response Time in TC1M based Systems (AP32076) tricore-tm-architecture-and-core
TriCore™ DSP Kernel Benchmarks (AP32073) tricore-tm-architecture-and-core
TriCore™ Pipeline Behaviour & Instruction Execution Timing (AP32071) tricore-tm-architecture-and-core
Introduction Presentation tricore-tm-architecture-and-core
Introduction tricore-tm-architecture-and-core
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