74AHCT138BQ: 3至8线路解码器/解复用器;反相

74AHC138;74AHCT138是高速硅栅CMOS器件,与低功耗肖特基TTL (LSTTL)针脚兼容。其规格符合JEDEC标准No. 7A。

74AHC138;74AHCT138是3至8线路解码器/解复用器。其接受三个二进制加权地址输入(A0、A1和A2),处于使能状态时提供在被选中时为低电平的八个互斥输出(Y0至Y7)。

有三个使能输入:两个低电平有效(E1和E2)输入和一个高电平有效(E3)输入。除非E1和E2为低电平且E3为高电平,否则每个输出都将是高电平。

该多路使能功能只需凭借四个74AHC138;74AHCT138器件和一个反相器, 即能将该器件轻松并行扩展为32选1(5线路至32线路)解码器。通过将某个低电平有效使能输入用作数据输入以及将剩下的使能输入用作选通,74AHC138;74AHCT138可以用作一个八输出解复用器。未使用的使能输入必须恒定地连接到其相应的高电平或低电平有效状态。

74AHCT138BQ: 产品结构框图
Outline 3d SOT763-1
数据手册 (1)
名称/描述Modified Date
3-to-8 line decoder/demultplexer; inverting (REV 4.0) PDF (119.0 kB) 74AHC_AHCT138 [English]02 Apr 2014
应用说明 (5)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Pin FMEA for AHC/AHCT family (REV 1.0) PDF (52.0 kB) AN11106 [English]04 Nov 2011
手册 (2)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x... (REV 1.1) PDF (191.0 kB) SOT763-1 [English]30 May 2016
包装 (1)
名称/描述Modified Date
DHVQFN16; Reel pack, SMD, 7" Q1/T1 standard product orientation Orderable part number ending ,115 or... (REV 2.0) PDF (191.0 kB) SOT763-1_115 [English]05 Jul 2016
IBIS
订购信息
型号状态Family功能VCC (V)说明Logic switching levelsPackage versionOutput drive capability (mA)tpd (ns)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AHCT138BQActiveAHC(T)Decoders/demultiplexers4.5 - 5.5TTL enabledTTLSOT763-1+/- 84.4low-40~1259313.862DHVQFN1616
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74AHCT138BQSOT763-1Reel 7" Q1/T1Active74AHCT138BQ,115 (9352 855 73115)AHT13874AHCT138BQAlways Pb-free84.96.621.51E811
3-to-8 line decoder/demultplexer; inverting 74AHCT138PW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Pin FMEA for AHC/AHCT family 74AHC_T_245_Q100
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
ahct138 IBIS model 74AHCT138PW
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x... NPIC6C596A_Q100
DHVQFN16; Reel pack, SMD, 7" Q1/T1 standard product orientation Orderable part number ending ,115 or... NPIC6C596A_Q100
74LVC138A
TFF1024HN