74AUP2G14GM: 低功耗双路施密特触发反相器 _ BDTIC 中国领先电子元器件代理商

74AUP2G14GM: 低功耗双路施密特触发反相器

74AUP2G14提供两个带施密特触发动作的反相缓冲器，其接受标准输入信号。该类器件能将缓慢变化的输入信号转换成清晰无抖动的输出信号。

该器件可确保整个0.8 V至3.6 V VCC范围内的极低静态和动态功耗。

该器件完全适合使用IOFF的局部掉电应用。IOFF电路可禁用输出，防止掉电时破坏性回流电流通过该器件。

输入针对正向和负向信号在不同点进行切换。正电压VT+和负电压VT-之差定义为输入迟滞电压VH.

74AUP2G14GM: 产品结构框图

Outline 3d SOT886

数据手册 (1)

名称/描述	Modified Date
Low-power dual Schmitt trigger inverter (REV 6.0) PDF (240.0 kB) 74AUP2G14 [English]	17 Sep 2015

应用说明 (4)

名称/描述	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]	06 May 2011
MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English]	30 Dec 2010
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]	30 Oct 2002

手册 (3)

名称/描述	Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]	13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

封装信息 (1)

名称/描述	Modified Date
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm (REV 1.0) PDF (189.0 kB) SOT886 [English]	08 Feb 2016

包装 (2)

名称/描述	Modified Date
XSON6; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering... (REV 2.0) PDF (205.0 kB) SOT886_115 [English]	23 Apr 2013
XSON6; reel pack; standard product orientation; 12NC ending 132 (REV 1.0) PDF (180.0 kB) SOT886_132 [English]	28 Nov 2012

支持信息 (2)

名称/描述	Modified Date
Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English]	30 Sep 2013
MAR_SOT886 Topmark (REV 1.0) PDF (73.0 kB) MAR_SOT886 [English]	03 Jun 2013

IBIS

aup2g14 IBIS model (REV 1.0) ibs AUP2G14 9/7/2015

订购信息

型号	状态	Family	V_CC (V)	功能	Logic switching levels	说明	Package version	Output drive capability (mA)	f_max (MHz)	t_pd (ns)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74AUP2G14GM	Active	AUP	1.1 - 3.6	Schmitt-triggers	CMOS	dual inverter Schmitt-trigger	SOT886	+/- 1.9	70	4.7	2	ultra low	-40~125	290	6.5	145	XSON6	6

封装环保信息

产品编号	封装说明	Outline Version	回流/波峰焊接	包装	产品状态	部件编号订购码 (12NC)	Marking	化学成分	RoHS / 无铅 / RHF	无铅转换日期	EFR	IFR(FIT)	MTBF（小时）	MSL	MSL LF
74AUP2G14GM		SOT886	Reflow_Soldering_Profile	Reel 7" Q1/T1, Q3/T4	Active	74AUP2G14GM,132 (9352 799 88132)	pK	74AUP2G14GM		Always Pb-free	0.0	3.29	3.04E8	1	1
74AUP2G14GM		SOT886	Reflow_Soldering_Profile	Reel 7" Q1/T1	Active	74AUP2G14GM,115 (9352 799 88115)	pK	74AUP2G14GM		Always Pb-free	0.0	3.29	3.04E8	1	1

Low-power dual Schmitt trigger inverter 74AUP2G14GX

Sorting through the low voltage logic maze 74LVC_H_245A_Q100

Pin FMEA for AUP family 74AUP1T34GW-Q100

MicroPak soldering information NTS0102_Q100

PicoGate Logic footprints NX3L4684

電圧レベルシフタ 74AVC16245DGG-Q100

NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100

Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100

MAR_SOT886 Topmark prtr5v0u2f

aup2g14 IBIS model 74AUP2G14GW

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm prtr5v0u2f

Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20

XSON6; reel pack; standard product orientation; 12NC ending 132 NCX2200GM

XSON6; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering... prtr5v0u2f

74LVC2G14

BGU8007

©1993 - 2024 BDTIC