74AUP2G57DP: Low-power dual PCB configurable multiple function gate

The 74AUP2G57 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

74AUP2G57DP: 产品结构框图

sot552-1_3d

数据手册 (1)

名称/描述	Modified Date
Low-power dual PCB configurable multiple function gate (REV 2.0) PDF (221.0 kB) 74AUP2G57 [English]	02 Dec 2015

手册 (5)

名称/描述	Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
Dual PCB configurable logic for more ways to save space and lower cost (REV 1.0) PDF (3.7 MB) 75017617_1 [English]	10 Nov 2014
NXP® Dual PCB Configurable Logic (REV 1.0) PDF (3.0 MB) 75017615 [English]	07 Nov 2014
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]	13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

选型工具指南 (2)

名称/描述	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

封装信息 (1)

名称/描述	Modified Date
plastic thin shri small outline package; 10 leads; body width 3 mm (REV 1.1) PDF (256.0 kB) SOT552-1 [English]	07 Jun 2016

包装 (1)

名称/描述	Modified Date
TSSOP10; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 1.0) PDF (269.0 kB) SOT552-1_118 [English]	16 Apr 2013

支持信息 (3)

名称/描述	Modified Date
Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English]	30 Sep 2013
Wave Soldering Profile (REV 1.0) PDF (20.0 kB) WAVE_SOLDERING_PROFILE [English]	30 Sep 2013
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

IBIS

74AUP2G57 IBIS model (REV 1.0) ibs AUP2G57 4/3/2015

订购信息

型号	状态	Family	功能	V_CC (V)	类型	Logic switching levels	说明	Output drive capability (mA)	Package version	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74AUP2G57DP	Active	AUP	dual configurable gate; Schmitt trigger	1.1 - 3.6	Configurable gates	CMOS	Configurable	+/- 1.9	SOT552-1	8.7	70	2	ultra low	-40~125	120	30.0		TSSOP10	10

封装环保信息

产品编号	封装说明	Outline Version	回流/波峰焊接	包装	产品状态	部件编号订购码 (12NC)	Marking	化学成分	RoHS / 无铅 / RHF	无铅转换日期	MSL	MSL LF
74AUP2G57DP		SOT552-1	Reflow_Soldering_Profile SSOP-TSSOP-VSO-WAVE Reflow_Soldering_Profile SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74AUP2G57DPJ (9353 044 71118)	aC	74AUP2G57DP		Always Pb-free	1	1
74AUP2G57DP		SOT552-1		Reel 7" Q3/T4, Reverse	Withdrawn	74AUP2G57DPH (9353 044 71125)	aC	74AUP2G57DP		Always Pb-free	1	1