74AUP3G34DC: Low-power triple buffer
The 74AUP3G34 is a triple buffer.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
74AUP3G34DC: 产品结构框图
Outline 3d SOT765-1
数据手册 (1)
手册 (1)
选型工具指南 (2)
封装信息 (1)
包装 (1)
IBIS
订购信息
型号 | 状态 | Family | 功能 | VCC (V) | 说明 | Logic switching levels | Package version | Output drive capability (mA) | fmax (MHz) | No of bits | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
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74AUP3G34DC | Active | AUP | triple buffer | 1.1 - 3.6 | triple buffer | CMOS | SOT765-1 | +/- 1.9 | 70 | 3 | 3.9 | ultra low | -40~125 | 203 | 34.1 | 113 | VSSOP8 | 8 |
封装环保信息
产品编号 | 封装说明 | Outline Version | 回流/波峰焊接 | 包装 | 产品状态 | 部件编号订购码 (12NC) | Marking | 化学成分 | RoHS / 无铅 / RHF | 无铅转换日期 | MSL | MSL LF |
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74AUP3G34DC | | SOT765-1 | | Reel 7" Q3/T4, Reverse | Active | 74AUP3G34DCH
(9352 806 94125) | Standard Marking | 74AUP3G34DC | | Always Pb-free | 1 | 1 |