74AXP1G32GN: Low-power 2-input OR gate

The 74AXP1G32 is a single 2-input OR gate.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.7 V to 2.75 V. It is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

74AXP1G32GN: 产品结构框图
Outline 3d SOT1115
数据手册 (1)
名称/描述Modified Date
Low-power 2-input OR gate (REV 1.0) PDF (184.0 kB) 74AXP1G32 [English]25 Aug 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
extremely thin small outline package; no leads; 6 terminals (REV 1.0) PDF (176.0 kB) SOT1115 [English]08 Feb 2016
支持信息 (1)
名称/描述Modified Date
MAR_SOT1115 Topmark (REV 1.0) PDF (47.0 kB) MAR_SOT1115 [English]03 Jun 2013
IBIS
订购信息
型号状态FamilyVCC (V)功能Logic switching levels说明类型Package versionOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AXP1G32GNActiveAXP0.7 - 2.75OR gatesCMOSsingle 2-input OR gateOR gatesSOT1115+/- 4.52.5701ultra low-40~8536628.6226XSON66
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期MSLMSL LF
74AXP1G32GNSOT1115Reel 7" Q3/T4, ReverseActive74AXP1G32GNH (9353 040 46125)Standard Marking74AXP1G32GNAlways Pb-free11
Low-power 2-input OR gate 74AXP1G32GX
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT1115 Topmark 74AUP1G332
74AXP1G32 IBIS model 74AXP1G32GX
SOT1115 74AUP1G332
74AVCM162836DGG
74LVC2G17