74LVC02A: 四路2输入或非门

74LVC02A提供四个2输入或非门。

输入可通过3.3 V或5 V器件进行驱动。该特性允许将这些器件用作混合3.3 V和5 V应用中的转换器。

74LVC02A: 产品结构框图
Outline 3d SOT337-1
数据手册 (1)
名称/描述Modified Date
Quad 2-input NOR gate (REV 8.0) PDF (158.0 kB) 74LVC02A [English]15 Dec 2011
应用说明 (5)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English]04 Feb 2011
Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English]05 Feb 2002
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]15 Sep 1995
手册 (3)
名称/描述Modified Date
Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English]10 Jul 2015
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
封装信息 (4)
名称/描述Modified Date
plastic small outline package; 14 leads; body width 3.9 mm (REV 1.0) PDF (166.0 kB) SOT108-1 [English]08 Feb 2016
plastic shrink small outline package; 14 leads; body width 5.3 mm (REV 1.0) PDF (295.0 kB) SOT337-1 [English]08 Feb 2016
plastic thin shrink small outline package; 14 leads; body width 4.4 mm (REV 1.0) PDF (285.0 kB) SOT402-1 [English]08 Feb 2016
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x... (REV 1.0) PDF (187.0 kB) SOT762-1 [English]08 Feb 2016
包装 (4)
名称/描述Modified Date
Standard product orientation 12NC ending 115 (REV 3.0) PDF (108.0 kB) SOT762-1_115 [English]09 Apr 2013
SO14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering... (REV 4.0) PDF (207.0 kB) SOT108-1_118 [English]08 Apr 2013
TSSOP14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 1.0) PDF (217.0 kB) SOT402-1_118 [English]08 Apr 2013
Standard product orientation 12NC ending 118 (REV 1.0) PDF (86.0 kB) SOT337-1_118 [English]04 Apr 2013
支持信息 (4)
名称/描述Modified Date
Footprint for reflow soldering (REV 1.0) PDF (9.0 kB) SO-SOJ-REFLOW [English]08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (8.0 kB) SO-SOJ-WAVE [English]08 Oct 2009
Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English]08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
IBIS
SPICE
订购信息
型号状态
74LVC02ADActive
74LVC02APWActive
74LVC02ADBActive
74LVC02ABQActive
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74LVC02APWSOT402-1SSOP-TSSOP-VSO-WAVEReel 13" Q1/T1Active74LVC02APW,118 (9352 500 10118)LVC02A74LVC02APWweek 10, 2005123.83.872.58E811
Bulk PackActive74LVC02APW,112 (9352 500 10112)LVC02A74LVC02APWweek 10, 2005123.83.872.58E811
74LVC02ADSOT108-1SO-SOJ-REFLOW SO-SOJ-WAVE
SO-SOJ-REFLOW SO-SOJ-WAVE
Reel 13" Q1/T1Active74LVC02AD,118 (9352 499 90118)74LVC02AD74LVC02ADweek 32, 2004123.83.872.58E811
Bulk PackActive74LVC02AD,112 (9352 499 90112)74LVC02AD74LVC02ADweek 32, 2004123.83.872.58E811
74LVC02ADBSOT337-1SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE
SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE
Reel 13" Q1/T1Active74LVC02ADB,118 (9352 500 00118)LVC02A74LVC02ADBweek 12, 2005123.83.872.58E811
Bulk PackActive74LVC02ADB,112 (9352 500 00112)LVC02A74LVC02ADBweek 12, 2005123.83.872.58E811
74LVC02ABQSOT762-1Reel 7" Q1/T1Active74LVC02ABQ,115 (9352 736 85115)VC02A74LVC02ABQAlways Pb-free123.83.872.58E811
Quad 2-input NOR gate 74LVC02APW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Pin FMEA for LVC family 74LVC1G123_Q100
Power considerations when using CMOS and BiCMOS logic devices 74AHCT244PW
Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
Low voltage CMOS family - LVC 74LVC_H_245A_Q100
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
lvc02a IBIS model 74LVC02APW
lvc Spice model 74LVC3G17GT
plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74LV164_Q100
TSSOP14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... 74LV164_Q100
plastic small outline package; 14 leads; body width 3.9 mm 74LV164_Q100
Footprint for reflow soldering NPIC6C596A_Q100
Footprint for wave soldering NPIC6C596A_Q100
SO14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering... 74LV164_Q100
plastic shrink small outline package; 14 leads; body width 5.3 mm 74LVC32A_Q100
Footprint for reflow soldering 74HC_T_595_Q100
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
Standard product orientation 12NC ending 118 74LVC32A_Q100
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x... 74LV164_Q100
Standard product orientation 12NC ending 115 74LV164_Q100
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