特性- Possible to receive the sampling frequency of 32kHz to 192kHz and 24 bits data at a maximum.
- Supports I2S data output that facilitates interfacing with DSP.
- Output clock: 512fs, 256fs, 128fs, 64fs, 32fs, 2fs, fs, and fs/2
- Possible to output oscillation amplifier and external input clocks regardless of the PLL status.
- Maintains output clock continuity during clock switching.
- Supports Multi-channel transfer and reception, using master/slave function.
- Possible to process demodulation functions using common low-jitter clock without using PLL(external clock synchronization function)
- Built-in PLL error lock prevention circuit to provide accurate lock
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