MC100EL91: Triple LVPECL/PECL Input to -5.0 V ECL Output Translator

The MC100EL91 is a triple PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and translates them to differential -5 V ECL output signals. (For translation to -3.3 V ECL output, see MC100LVEL91.)To accomplish the level translation, the EL91 requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GND pins are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01 µF capacitors. Under open input conditions, the Dbar input will be biased at VCC/2 and the D input will be pulled to GND. This condition will force the Q output to a low, ensuring stability. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

特性

670 ps Typical Propagation Delay
ESD Protection: >2 KV HBM, >200 V MM
The 100 Series Contains Temperature Compensation
Operating Range: VCC = 4.75 V to 5.25 V; VEE = -4.2 V to -5.5 V; GND= 0 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 282 devices
Pb-Free Packages are Available

封装

应用注释 (17)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit	AN1503/D (120.0kB)	6
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
5 V Triple PECL Input to -5 V ECL Output Translator	MC100EL91/D (144kB)	8	Jul, 2016

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for mc100el91dw at 5VCC, -5VEE	MC100EL91DW_5_-5.IBS (6.0kB)	3

封装图纸 (1)

Document Title	Document ID/Size	Revision
SOIC-20 WB	751D-05 (36.3kB)	H

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100EL91DWG	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tube	38	联系BDTIC
MC100EL91DWR2G	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tape and Reel	1000	联系BDTIC