MC100EP016A: ECL 8-Bit Synchronous Binary Counter _ BDTIC 中国领先电子元器件代理商

MC100EP016A: ECL 8-Bit Synchronous Binary Counter

The MC100EP016A is a high-speed synchronous, presettable, cascadeable 8-bit binary counter. Architecture and operation are the same as the MC100E016 in the ECLinPS family.The counter features internal feedback to TCbar gated by the TCLD (Terminal Count Load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the TCbar feedback is disabled, and counting proceeds continuously, with TCbar going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated. COUT and COUTbar provide differential outputs from a single, non-cascaded counter or divider application. COUT and COUTbar should not be used in cascade configuration. Only TCbar should be used for a counter or divider cascade chain output. A differential clock input has also been added to improve performance. The 100 Series contains temperature compensation.

特性

550 ps Typical Propagation Delay
Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016
PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
Open Input Default State
Safety Clamp on Clock Inputs
Internal TCbar Feedback (Gated)
Addition of COUT and COUTbar
8-bit
Differential Clock Input
VBB Output
Fully Synchronous Counting and TCbar Generation
Asynchronous Master Reset
Pb-Free Packages are Available

应用

Hi-Speed Binary Counting

封装

应用注释 (14)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3V ECL 8-Bit Synchronous Binary Up Counter	MC100EP016A/D (132.0kB)	9

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for MC100EP016A_33V	MC100EP016A_33V.IBS (11kB)	2	Oct, 2016

封装图纸 (1)

Document Title	Document ID/Size	Revision
QFN32, 5x5, 0.5P, 3.1x3.1EP	488AM (57.4kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100EP016AFAG	Active	Pb-free Halide free	LQFP-32	联系BDTIC	2	Tray JEDEC	250	联系BDTIC
MC100EP016AFAR2G	Active	Pb-free Halide free	LQFP-32	联系BDTIC	2	Tape and Reel	2000	联系BDTIC
MC100EP016AMNG	Active	Pb-free Halide free	QFN-32	488AM	1	Tube	74	联系BDTIC
MC100EP016AMNR4G	Active	Pb-free Halide free	QFN-32	488AM	1	Tape and Reel	1000	联系BDTIC

订购产品技术参数

Product	Type	Input Level	Output Level	VCC Typ (V)	fMax Typ (MHz)	tpd Typ (ns)	tR & tF Max (ps)
MC100EP016AFAG	Counter	CML ECL	ECL	3.3	1400	0.55	320
MC100EP016AFAR2G	Counter	CML ECL	ECL	3.3	1400	0.55	320
MC100EP016AMNG	Counter	CML ECL	ECL	3.3	1400	0.55	320
MC100EP016AMNR4G	Counter	ECL CML	ECL	3.3	1400	0.55	320