MC100EP116: Differential Line Receiver / Driver _ BDTIC 中国领先电子元器件代理商

MC100EP116: Differential Line Receiver / Driver

The MC10EP116/100EP116 is a 6-bit differential line receiver based on the EP16 device. The 3.0GHz bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.The differential inputs have internal clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state. Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device. Note that the input clamp will take affect only if both inputs fall 2.5V below VCC.The 100 Series contains temperature compensation.

特性

260 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE =-3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output will default LOW with inputs open or at VEE
VBB Output

应用

General Purpose Logic

封装

应用注释 (15)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3V / 5V Hex Differential Line Receiver / Driver	MC10EP116/D (173.0kB)	11

仿真模型 (4)

Document Title	Document ID/Size	Revision
IBIS Model for MC100EP116FA with VCC-0.0 V and VEE=-5.0 V	MC100EP116FA_-50.IBS (7.0kB)	1
IBIS Model for mc100ep116fa -3.3V	MC100EP116FA_-33.IBS (6.0kB)	1.0
IBIS Model for mc100ep116fa 5.0 V	MC100EP116FA_50V.IBS (7.0kB)	1
IBS Model for MC100EP116FA 3.3V	MC100EP116FA_33V.IBS (7.0kB)	1

封装图纸 (1)

Document Title	Document ID/Size	Revision
QFN32, 5x5, 0.5P, 3.1x3.1EP	488AM (57.4kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100EP116FAG	Active	Pb-free Halide free	LQFP-32	联系BDTIC	2	Tray JEDEC	250	联系BDTIC
MC100EP116FAR2G	Active	Pb-free Halide free	LQFP-32	联系BDTIC	2	Tape and Reel	2000	联系BDTIC
MC100EP116MNG	Lifetime	Pb-free Halide free	QFN-32	488AM	1	Tube	74
MC100EP116MNR4G	Lifetime	Pb-free Halide free	QFN-32	488AM	1	Tape and Reel	1000