MC100EPT21: Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator

The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal. The VBB output allows the EPT21 to be cap coupled in either single-ended or differential input mode. When single-ended cap coupled, VBB output tied to the D0 input for a non-inverting buffer or the D0 input for an inverting buffer. When cap coupled differentially, VBB output is connected through a resistor to each input pin. If used, the VBB pin should be bypassed to VCC via a 0.01 F capacitor. For additional information see AND8020. For a single-ended direct connection use an external voltage reference source such as a resistor divider. Do not use VBB for a single-ended direct connection.

特性

1.4ns Typical Propagation Delay
Maximum Frequency > 275 MHz Typical
24mA TTL outputs
LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
The 100 Series Contains Temperature Compensation
VBB Output
New Differential Input Common Mode Range

应用

Precision Clock Translation

封装

应用注释 (18)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
EPT Spice Modeling Kit	AND8014/D (63.0kB)	0
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
Translator, Differential LVPECL to LVTTL	MC100EPT21/D (127.0kB)	22

仿真模型 (2)

Document Title	Document ID/Size	Revision	Revision Date
EPT21/23/25 ECLinPS PlusE Translator TTL output SPICE Modeling Kit	AND8118/D (53.0kB)	0
IBS Model for MC100EPT21D (3.3V)	MC100EPT21D_33.IBS (7.0kB)	4

封装图纸 (3)

Document Title	Document ID/Size	Revision
DFN8 2.0x2.0x0.9mm, 0.5p	506AA (31.8kB)	F
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100EPT21DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	联系BDTIC
MC100EPT21DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	联系BDTIC
MC100EPT21DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	联系BDTIC
MC100EPT21DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	联系BDTIC
MC100EPT21MNR4G	Active	Pb-free Halide free	DFN-8	506AA	1	Tape and Reel	1000	联系BDTIC

订购产品技术参数

Product	Channels	Input Level	Output Level	VCC Typ (V)	fMax Typ (MHz)	tpd Typ (ns)	tR & tF Max (ps)
MC100EPT21DG	1	LVDS ECL CML	TTL	3.3	350	1.4	900
MC100EPT21DR2G	1	ECL CML LVDS	TTL	3.3	350	1.4	900
MC100EPT21DTG	1	CML LVDS ECL	TTL	3.3	350	1.4	900
MC100EPT21DTR2G	1	CML LVDS ECL	TTL	3.3	350	1.4	900
MC100EPT21MNR4G	1	ECL CML LVDS	TTL	3.3	350	1.4	900