MC100EPT26: Translator, 1:2 Fanout Differential LVPECL / LVDS to LVTTL

The MC100EPT26 is a 1:2 Fanout Differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the 1:2 fanout design of the EPT26 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed PC board.The VBB output allows the EPT26 to be used in a single-ended input mode. In this mode the VBB output is tied to the D0bar input for a non-inverting buffer or the D0 input for an inverting buffer. If used, the VBB pin should be bypassed to ground via a 0.01 uF capacitator.

特性

1.4ns Typical Propagation Delay
Maximum Frequency > 275 MHz Typical
The 100 Series Contains Temperature Compensation
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
Open Input Default State
Safety Clamp on Inputs
24mA TTL outputs
Q Outputs will default LOW with inputs open or at VEE
VBB Output
Pb-Free Packages are Available

封装

应用注释 (18)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
EPT Spice Modeling Kit	AND8014/D (63.0kB)	0
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3 V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator	MC100EPT26/D (159kB)	17	Aug, 2016

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
IBS Model for MC100EPT26D 3.3 V	MC100EPT26D_33.IBS (7.0kB)	3

封装图纸 (3)

Document Title	Document ID/Size	Revision
DFN8 2.0x2.0x0.9mm, 0.5p	506AA (31.8kB)	F
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100EPT26DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	联系BDTIC
MC100EPT26DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	联系BDTIC
MC100EPT26DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	联系BDTIC
MC100EPT26DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	联系BDTIC
MC100EPT26MNR4G	Active	Pb-free Halide free	DFN-8	506AA	1	Tape and Reel	1000	联系BDTIC

订购产品技术参数

Product	Channels	Input Level	Output Level	VCC Typ (V)	fMax Typ (MHz)	tpd Typ (ns)	tR & tF Max (ps)
MC100EPT26DG	1	ECL	TTL	3.3	350	1.5	950
MC100EPT26DR2G	1	ECL	TTL	3.3	350	1.5	950
MC100EPT26DTG	1	ECL	TTL	3.3	350	1.5	950
MC100EPT26DTR2G	1	ECL	TTL	3.3	350	1.5	950
MC100EPT26MNR4G	1	ECL	TTL	3.3	350	1.5	950