MC100LVEL11: ECL 1:2 Differential Clock/Data Fanout Buffer

The MC100LVEL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times significantly improved over the E111, the LVEL11 is ideally suited for those applications which require the ultimate in AC performance. The differential inputs of the LVEL11 employ clamping circuitry to maintain stability under open input conditions. If the inputs are left open (pulled to VEE) the Q outputs will go LOW.

特性
  • 330 ps Propagation Delay
  • 5 ps Skew Between Outputs
  • High Bandwidth Output Transitions
  • ESD Protection: >4 KV HBM, >200 V MM
  • The 100 Series Contains Temperature Compensation
  • PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE = -3.0 V to -3.8 V
  • Internal Input Pulldown Resistors
  • Q Output will Default LOW with Inputs Open or at VEE
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 63 devices
封装
应用注释 (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V ECL 1:2 Differential Fanout BufferMC100LVEL11/D (93kB)13
仿真模型 (5)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100LVEL11D 3.3VMC100LVEL11D_33.IBS (14.0kB)6
IBIS Model for MC100LVEL11MN at 3.3VMC100LVEL11MN_33.IBS (5.0kB)1
IBIS Model for mc100lvel11d -3.3MC100LVEL11D_-33.IBS (7.0kB)8
IBIS model for mc100lvel11dt 3.3VMC100LVEL11DT_33.IBS (5.0kB)5
Low Voltage ECLinPS SPICE Modeling KitAN1560/D (88.0kB)5
封装图纸 (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC100LVEL11DGActivePb-free Halide freeSOIC-8751-071Tube98联系BDTIC
MC100LVEL11DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500联系BDTIC
MC100LVEL11DTGActivePb-free Halide freeTSSOP-8948R-023Tube100联系BDTIC
MC100LVEL11DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500联系BDTIC
MC100LVEL11MNR4GActivePb-free Halide freeDFN-8506AA1Tape and Reel1000联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100LVEL11DGBuffer11:2LVDS ECLECL3.30.6200.333201000
MC100LVEL11DR2GBuffer11:2ECL LVDSECL3.30.6200.333201000
MC100LVEL11DTGBuffer11:2ECL LVDSECL3.30.6200.333201000
MC100LVEL11DTR2GBuffer11:2LVDS ECLECL3.30.6200.333201000
MC100LVEL11MNR4GBuffer11:2ECL LVDSECL3.30.6200.333201000
3.3V ECL 1:2 Differential Fanout Buffer (93kB) MC100LVEL11
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100LVEL11D 3.3V MC100LVEL11
IBIS Model for MC100LVEL11MN at 3.3V MC100LVEL11
IBIS Model for mc100lvel11d -3.3 MC100LVEL11
IBIS model for mc100lvel11dt 3.3V MC100LVEL11
Low Voltage ECLinPS SPICE Modeling Kit MC100LVELT23
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220