MC100LVEL33: 3.3 V ECL ÷·4 Divider _ BDTIC 中国领先电子元器件代理商

MC100LVEL33: 3.3 V ECL ÷·4 Divider

The MC100LVEL33 is an integrated div by 4 divider. The LVEL is functionally equivalent to the EL33 and works from a 3.3 V supply.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple LVEL33's in a system. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

特性

630ps Propagation Delay
4.0 GHz Typical Maximum Frequency
ESD Protection: >4 KV HBM, >200 V MM
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V
NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -3.8 V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 130 devices
Pb-Free Packages are Available

应用

Phase-Locked Loops

封装

应用注释 (15)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3 V ECL Divide by 4 Divider	MC100LVEL33/D (153kB)	6	Jul, 2016

仿真模型 (3)

Document Title	Document ID/Size	Revision
IBIS Model for MC100LVEL33D 3.3V VCC	MC100LVEL33D_33.IBS (7.0kB)	2
IBIS Model for mc100lvel33 VEE at -3.3 V	MC100LVEL33D_-33.IBS (7.0kB)	2
Low Voltage ECLinPS SPICE Modeling Kit	AN1560/D (88.0kB)	5

封装图纸 (2)

Document Title	Document ID/Size	Revision
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100LVEL33DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	联系BDTIC
MC100LVEL33DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	联系BDTIC
MC100LVEL33DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	联系BDTIC
MC100LVEL33DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	联系BDTIC

订购产品技术参数

Product	Type	Input Level	Output Level	VCC Typ (V)	fMax Typ (MHz)	tpd Typ (ns)	tR & tF Max (ps)
MC100LVEL33DG	Divider	ECL LVDS	ECL	3.3	4000	0.67	320
MC100LVEL33DR2G	Divider	ECL LVDS	ECL	3.3	4000	0.67	320
MC100LVEL33DTG	Divider	ECL LVDS	ECL	3.3	4000	0.67	320
MC100LVEL33DTR2G	Divider	LVDS ECL	ECL	3.3	4000	0.67	320