MC100LVEL40: Phase - Frequency Detector, Differential, ECL, 3.3 V / 5.0 V

The MC100LVEL40 is a three state phase frequency-detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate of the R and V inputs should be less than 5 ns. The device is designed to work with a 3.3 V power supply.When the reference (R) and the feedback (FB) inputs are unequal in frequency and/or phase the differential up (U) and down (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.For application information, see AND8040/D, "Phase Lock Loop Operation."The 100 Series Contains Temperature Compensation

特性

250MHz Typical Bandwidth
ESD Protection: >2 KV HBM
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 356 devices
Pb-Free Packages are Available

封装

应用注释 (15)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3/5V ECL Differential Phase-Frequency Detector	MC100LVEL40/D (114.0kB)	8

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
Low Voltage ECLinPS SPICE Modeling Kit	AN1560/D (88.0kB)	5

封装图纸 (1)

Document Title	Document ID/Size	Revision
SOIC-20 WB	751D-05 (36.3kB)	H

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100LVEL40DWG	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tube	38	联系BDTIC
MC100LVEL40DWR2G	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tape and Reel	1000	联系BDTIC