MC100LVEP16: Differential Driver / Receiver

The MC10LVEP16 is a world-class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16 and LVEL16, the LVEP16 is ideally suited for interfacing with high frequency and low voltage (2.5 V) sources. Single ended input operation is limited to a VCC >= 3.0 V in PECL mode, or VEE <= 3.0 V in NECL mode.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation.

特性
  • 240 ps Propagation Delay
  • Maximum Frequency > 4 GHz Typical
  • PECL Mode Operating Range: VCC= 2.375 V to 3.8 V with VEE=0 V
  • NECL Mode Operating Range: VCC=0 V with VEE= -2.375 V to -3.8 V
  • VBB Output
  • Open Input Default State
  • LVDS Input Compatible
封装
应用注释 (17)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5 V / 3.3 V ECL Differential Receiver/DriverMC10LVEP16/D (191kB)12Aug, 2016
仿真模型 (4)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100LVEP16D -2.5VEEMC100LVEP16D_-25V.IBS (10.0kB)3
IBIS Model for MC100LVEP16D -3.3VEEMC100LVEP16D_-33V.IBS (9.0kB)3
IBIS Model for MC100LVEP16D 2.5VCCMC100LVEP16D_25V.IBS (10.0kB)3
IBIS Model for MC100LVEP16D 3.3VCCMC100LVEP16D_33V.IBS (9.0kB)4
封装图纸 (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价）
MC100LVEP16DGActivePb-free Halide freeSOIC-8751-071Tube98联系BDTIC
MC100LVEP16DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500联系BDTIC
MC100LVEP16DTGActivePb-free Halide freeTSSOP-8948R-023Tube100联系BDTIC
MC100LVEP16DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500联系BDTIC
MC100LVEP16MNR4GActivePb-free Halide freeDFN-8506AA1Tape and Reel1000联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100LVEP16DGSignal Driver11:1ECL CML LVDSECL3.3 2.50.147200.241704000
MC100LVEP16DR2GSignal Driver11:1ECL CML LVDSECL3.3 2.50.147200.241704000
MC100LVEP16DTGSignal Driver11:1LVDS CML ECLECL2.5 3.30.147200.241704000
MC100LVEP16DTR2GSignal Driver11:1ECL LVDS CMLECL2.5 3.30.147200.241704000
MC100LVEP16MNR4GSignal Driver11:1LVDS CML ECLECL3.3 2.50.147200.241704000
2.5 V / 3.3 V ECL Differential Receiver/Driver (191kB) MC10LVEP16
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100LVEP16D -2.5VEE MC100LVEP16
IBIS Model for MC100LVEP16D -3.3VEE MC100LVEP16
IBIS Model for MC100LVEP16D 2.5VCC MC100LVEP16
IBIS Model for MC100LVEP16D 3.3VCC MC100LVEP16
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220
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