MC10ELT24: TTL to Differential ECL Translator

The MC10ELT/100ELT24 is a TTL to differential ECL translator. Because ECL levels are used a +5V, -5.2V (or -4.5V) and ground are required. The small 8-lead package and the single gate of the ELT24 makes it ideal for those applications where space, performance and low power are at a premium. The 100 Series contains temperature compensation.

特性
  • 0.8 ns TPHL, 0.95 ns TPLH Typical Propagation Delay
  • PNP TTL Inputs for Minimal Loading
  • Flow Through Pinouts
  • ESD Protection: >4 KV HBM, >200 V MM
  • Operating Range: VCC= 4.5 V to 5.5 V; VEE= -4.2 V to -5.5 V with GND= 0 V
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 51 devices
  • Pb-Free Packages are Available
应用注释 (17)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Lite Translator ELT Family SPICE I/O Model KitAN1596/D (189.0kB)2
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Translator, TTL to Differential ECLMC10ELT24/D (88kB)11
仿真模型 (2)
Document TitleDocument ID/SizeRevisionRevision Date
AN1596-D SPICE I/O Model Kit for ELT Family DevicesAN1596-D.PDF (189.0kB)2
IBIS Model for mc10elt24dMC10ELT24D.IBS (5.0kB)3
封装图纸 (2)
Document TitleDocument ID/SizeRevision
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价）
MC10ELT24DGActivePb-free Halide freeSOIC-8751-071Tube98联系BDTIC
MC10ELT24DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500联系BDTIC
MC10ELT24DTGLast ShipmentsPb-free Halide freeTSSOP-8948R-023Tube100
订购产品技术参数
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC10ELT24DG1TTLECL54000.951250
MC10ELT24DR2G1TTLECL54000.951250
Translator, TTL to Differential ECL (88kB) MC10ELT24
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit MC10ELT28
IBIS Model for mc10elt24d MC10ELT24
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
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