MC10EP05: 3.3 V / 5.0 V 2-Input Differential AND/NAND Gate
The MC10/100EP05 is a 2-input differential AND/NAND gate.The device is functionally equivalent to the EL05 and LVEL05devices. With AC performance much faster than the LVEL05 device,the EP05 is ideal for applications requiring the fastest AC performance available.The 100 Series contains temperature compensation.
特性
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封装
应用注释 (16)
数据表 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| 3.3 V / 5 V 2-Input Differential AND/NAND | MC10EP05/D (184kB) | 10 | Jul, 2016 |
仿真模型 (4)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| IBIS Model for MC10EP05D -3.3V | MC10EP05D_-33.IBS (5.0kB) | 1 | |
| IBIS Model for MC10EP05D -5.2V | MC10EP05D_-52.IBS (5.0kB) | 2 | |
| IBIS Model for MC10EP05D 3.3V | MC10EP05D_33.IBS (5.0kB) | 2 | |
| IBIS Model for MC10EP05D 5.0V | MC10EP05D_50.IBS (5.0kB) | 2 |
封装图纸 (2)
| Document Title | Document ID/Size | Revision |
|---|---|---|
| SOIC-8 Narrow Body | 751-07 (62.6kB) | AK |
| TSSOP 8 3.0x3.0x0.95 mm | 948R-02 (77.3kB) | A |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| MC10EP05DG | Active | Pb-free Halide free | SOIC-8 | 751-07 | 1 | Tube | 98 | 联系BDTIC |
| MC10EP05DR2G | Active | Pb-free Halide free | SOIC-8 | 751-07 | 1 | Tape and Reel | 2500 | 联系BDTIC |
| MC10EP05DTG | Active | Pb-free Halide free | TSSOP-8 | 948R-02 | 3 | Tube | 100 | 联系BDTIC |
| MC10EP05DTR2G | Lifetime | Pb-free Halide free | TSSOP-8 | 948R-02 | 3 | Tape and Reel | 2500 | |
订购产品技术参数
| Product | Type | Channels | Input Level | Output Level | VCC Typ (V) | fToggle Max (MHz) | tpd Typ (ns) | tJitter Typ (ps) | tR & tF Max (ps) |
|---|---|---|---|---|---|---|---|---|---|
| MC10EP05DG | AND/NAND | 1 | ECL CML | ECL | 5 3.3 | 3000 | 0.22 | 0.2 | 170 |
| MC10EP05DR2G | AND/NAND | 1 | ECL CML | ECL | 3.3 5 | 3000 | 0.22 | 0.2 | 170 |
| MC10EP05DTG | AND/NAND | 1 | ECL CML | ECL | 5 3.3 | 3000 | 0.22 | 0.2 | 170 |
- AC Characteristics of ECL Devices NB100LVEP91
- Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
- Designing with PECL (ECL at +5.0 V) NB100LVEP91
- ECL Clock Distribution Techniques NB100LVEP91
- ECLinPS Plus™ Spice Modeling Kit MC10EPT20
- ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
- Interfacing Between LVDS and ECL NB100ELT23L
- Interfacing with ECLinPS NB100LVEP91
- Metastability and the ECLinPS Family MC10EPT20
- Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
- Phase Lock Loop General Operations MC10H604
- Storage and Handling of Drypack Surface Mount Device NB3U23C
- Termination of ECL Logic Devices NB100LVEP91
- The ECL Translator Guide NB100LVEP91
- Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
- Using Wire-OR Ties in ECLInPS™ Designs MC10H351
- IBIS Model for MC10EP05D -3.3V MC10EP05
- IBIS Model for MC10EP05D -5.2V MC10EP05
- IBIS Model for MC10EP05D 3.3V MC10EP05
- IBIS Model for MC10EP05D 5.0V MC10EP05
- SOIC-8 Narrow Body CM1216
- TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
