MC10EP32: 3.3 V / 5.0 V ECL ÷·2 Divider _ BDTIC 中国领先电子元器件代理商

MC10EP32: 3.3 V / 5.0 V ECL ÷·2 Divider

The MC10/100EP32 is an integrated divide by 2 divider with differential CLK inputs.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01μF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBB should be left open.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EP32's in a system.The 100 Series contains temperature compensation.

特性

350ps Typical Propagation Delay
Maximum Frequency > 4 GHz Typical
PECL Mode Operating Range: VCC= 3.0 V to 5.5 Vwith VEE= 0 V
NECL Mode Operating Range: VCC= 0 Vwith VEE= –3.0 V to –5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output will default LOW with inputs open or at VEE
Pb-Free Packages are Available

应用

Reduce System clock skew over the alternative CMOS and TTL technologies.

封装

应用注释 (16)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3 V / 5 V ECL Divide by 2 Divider	MC10EP32/D (191kB)	12	Jul, 2016

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for MC10EP32D 3.3V	MC10EP32D_33.IBS (5.0kB)	1

封装图纸 (3)

Document Title	Document ID/Size	Revision
DFN8 2.0x2.0x0.9mm, 0.5p	506AA (31.8kB)	F
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC10EP32DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	联系BDTIC
MC10EP32DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	联系BDTIC
MC10EP32DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	联系BDTIC
MC10EP32DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	联系BDTIC
MC10EP32MNR4G	Active	Pb-free Halide free	DFN-8	506AA	1	Tape and Reel	1000	联系BDTIC

订购产品技术参数

Product	Type	Input Level	Output Level	VCC Typ (V)	fMax Typ (MHz)	tpd Typ (ns)	tR & tF Max (ps)
MC10EP32DG	Divider	ECL CML	ECL	5 3.3	4000	0.35	150
MC10EP32DR2G	Divider	CML ECL	ECL	5 3.3	4000	0.35	150
MC10EP32DTG	Divider	CML ECL	ECL	5 3.3	4000	0.35	150
MC10EP32DTR2G	Divider	ECL CML	ECL	5 3.3	4000	0.35	150
MC10EP32MNR4G	Divider	CML ECL	ECL	5 3.3	4000	0.35	150