MC10H102: Quad 2-Input NOR Gate
The MC10H102 is a quad 2-input NOR gate. The MC10H102 provides one gate with OR/NOR outputs. This MECL 10H part is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in propagation delay, and no increases in power- supply current.
特性
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封装
应用注释 (16)
数据表 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| Quad 2-Input NOR Gate | MC10H102/D (133kB) | 8 | Aug, 2016 |
仿真模型 (3)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| IBIS Model for MC10H102L | MC10H102L.IBS (6.0kB) | 0 | |
| IBIS Model for MC10H102P | MC10H102P.IBS (6.0kB) | 0 | |
| MECL 10H SPICE Kit for Berkeley SPICE (PSPICE) | AN1578/D (161.0kB) | 0 |
封装图纸 (2)
| Document Title | Document ID/Size | Revision |
|---|---|---|
| 20 LEAD PLLC | 775-02 (60.9kB) | F |
| PDIP-16 | 648-08 (34.2kB) | V |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| MC10H102FNR2G | Active | Pb-free Halide free | PLLC-20 | 775-02 | 3 | Tape and Reel | 500 | 联系BDTIC |
| MC10H102PG | Active | Pb-free Halide free | PDIP-16 | 648-08 | NA | Tube | 25 | 联系BDTIC |
订购产品技术参数
| Product | Type | Channels | Input Level | Output Level | VCC Typ (V) | fToggle Max (MHz) | tpd Typ (ns) | tJitter Typ (ps) | tR & tF Max (ps) |
|---|---|---|---|---|---|---|---|---|---|
| MC10H102FNR2G | NOR | 4 | ECL | ECL | -5.2 | 1 | 1500 | ||
| MC10H102PG | NOR | 4 | ECL | ECL | -5.2 | 1 | 1500 |
- Quad 2-Input NOR Gate (133kB) MC10H102
- AC Characteristics of ECL Devices NB100LVEP91
- Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
- Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
- Designing with PECL (ECL at +5.0 V) NB100LVEP91
- ECL Clock Distribution Techniques NB100LVEP91
- ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
- Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
- Interfacing Between LVDS and ECL NB100ELT23L
- Interfacing with ECLinPS NB100LVEP91
- Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
- Phase Lock Loop General Operations MC10H604
- Storage and Handling of Drypack Surface Mount Device NB3U23C
- Termination of ECL Logic Devices NB100LVEP91
- The ECL Translator Guide NB100LVEP91
- Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
- Using Wire-OR Ties in ECLInPS™ Designs MC10H351
- IBIS Model for MC10H102L MC10H102
- IBIS Model for MC10H102P MC10H102
- MECL 10H SPICE Kit for Berkeley SPICE (PSPICE) MC100LVEL56
- 20 LEAD PLLC MC10H351
- PDIP-16 MC10H350
