MC10H350: PECL to TTL Translator
The MC10H350 is a member of the 10H family of high performance ECL logic. It consists of 4 translators with differential inputs and TTL outputs. The 3-state outputs can be disabled by applying a HIGH TTL logic level on the common OE input. The MC10H350 is designed to be used primarily in systems incorporating both ECL and TTL logic operating off a common power supply. The separate VCC power pins are not connected internally and thus isolate the noisy TTL VCC runs from the relatively quiet ECL VCC runs on the printed circuit board. The differential inputs allow the H350 to be used as an inverting or noninverting translator, or a differential line receiver. The H350 can also drive CMOS with the addition of a pullup resistor.
特性
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封装
应用注释 (15)
数据表 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| PECL to TTL Translator | MC10H350/D (139kB) | 11 | Aug, 2016 |
仿真模型 (2)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| H124, 125, 350-352 Translator I/O SPICE Modelling Kit | AN1598/D (105.0kB) | 1 | |
| IBIS Model for mc10h350p | MC10H350P.IBS (5.0kB) | 1 |
封装图纸 (2)
| Document Title | Document ID/Size | Revision |
|---|---|---|
| 20 LEAD PLLC | 775-02 (60.9kB) | F |
| PDIP-16 | 648-08 (34.2kB) | V |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| MC10H350FNG | Active | Pb-free Halide free | PLLC-20 | 775-02 | 3 | Tube | 46 | 联系BDTIC |
| MC10H350FNR2G | Active | Pb-free Halide free | PLLC-20 | 775-02 | 3 | Tape and Reel | 500 | 联系BDTIC |
| MC10H350PG | Active | Pb-free Halide free | PDIP-16 | 648-08 | NA | Tube | 25 | 联系BDTIC |
订购产品技术参数
| Product | Channels | Input Level | Output Level | VCC Typ (V) | fMax Typ (MHz) | tpd Typ (ns) | tR & tF Max (ps) |
|---|---|---|---|---|---|---|---|
| MC10H350FNG | 4 | ECL | TTL | 5 | 50 | 3.5 | 1600 |
| MC10H350FNR2G | 4 | ECL | TTL | 5 | 50 | 3.5 | 1600 |
| MC10H350PG | 4 | ECL | TTL | 5 | 50 | 3.5 | 1600 |
- PECL to TTL Translator (139kB) MC10H350
- AC Characteristics of ECL Devices NB100LVEP91
- Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
- Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
- Designing with PECL (ECL at +5.0 V) NB100LVEP91
- ECL Clock Distribution Techniques NB100LVEP91
- ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
- Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
- Interfacing Between LVDS and ECL NB100ELT23L
- Interfacing with ECLinPS NB100LVEP91
- Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
- Phase Lock Loop General Operations MC10H604
- Storage and Handling of Drypack Surface Mount Device NB3U23C
- Termination of ECL Logic Devices NB100LVEP91
- The ECL Translator Guide NB100LVEP91
- Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
- H124, 125, 350-352 Translator I/O SPICE Modelling Kit MC10H351
- IBIS Model for mc10h350p MC10H350
- 20 LEAD PLLC MC10H351
- PDIP-16 MC10H350
