MC10H600: 9-Bit TTL-ECL Translator _ BDTIC 中国领先电子元器件代理商

MC10H600: 9-Bit TTL-ECL Translator

The MC10H/100H600 is a 9-bit, dual supply TTL to ECL translator. Devices in the 9-bit translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The H600 features both ECL and TTL logic enable controls for maximum flexibility. The 10H version is compatible with MECL 10H ECL logic levels. The 100H version is compatible with 100K levels.

特性

9-Bit Ideal for Byte-Parity Applications
Flow-Through Configuration
Extra TTL and ECL Power/Ground Pins to Minimize Switching Noise
ECL and TTL Enable Inputs
Dual Supply
3.5 ns Max D to Q
PNP TTL Inputs for Low Loading
Choice of ECL Compatibility: MECL 10H (10Hxxx) or 100K (100Hxxx)
Pb-Free Packages are Available

封装

应用注释 (15)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Family Characteristics for MECL 10H™ and MECL 10K™	TND309/D (248.0kB)	1
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
MC10/100H60x Translator Family I/O SPICE Modelling Kit	AN1402/D (159.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5