MC10LVEP11: Clock / Data Fanout Buffer, 1:2 Differential, ECL, 2.5 V / 3.3 V

The MC10LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for applications requiring lower voltage. Single ended CLK input operation is limited to a VCC >= 3.0 V in PECL mode, or VEE <= -3.0 V in NECL mode.The 100 Series contains temperature compensation.

特性

240 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC= 2.375 V to 3.8 V with VEE= 0 V
NECL Mode Operating Range: VCC= 0 V with VEE= -2.375 V to -3.8 V
Open Input Default State
Q Outputs will default LOW with inputs open or at VEE
LVDS Input Compatible

应用

GbE or Fibre Channel Redundant Fan-out

封装

应用注释 (14)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
2.5 V / 3.3 V ECL 1:2 Differential Fanout Buffer	MC10LVEP11/D (243kB)	14	Aug, 2016

仿真模型 (2)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for mc10lvep11d 3.3V	MC10LVEP11D_33.IBS (5.0kB)	2
IBIS Model for mc10lvep11dt 3.3V	MC10LVEP11DT_33.IBS (5.0kB)	2

封装图纸 (2)

Document Title	Document ID/Size	Revision
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC10LVEP11DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	联系BDTIC
MC10LVEP11DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	联系BDTIC
MC10LVEP11DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	联系BDTIC
MC10LVEP11DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	联系BDTIC

订购产品技术参数

Product	Type	Channels	Input / Output Ratio	Input Level	Output Level	VCC Typ (V)	tJitterRMS Typ (ps)	tskew(o-o) Max (ps)	tpd Typ (ns)	tR & tF Max (ps)	fmaxClock Typ (MHz)
MC10LVEP11DG	Buffer	1	1:2	ECL LVDS CML	ECL	3.3 2.5	1.42	20	0.24	170	3000
MC10LVEP11DR2G	Buffer	1	1:2	ECL CML LVDS	ECL	3.3 2.5	1.42	20	0.24	170	3000
MC10LVEP11DTG	Buffer	1	1:2	CML ECL LVDS	ECL	3.3 2.5	1.42	20	0.24	170	3000
MC10LVEP11DTR2G	Buffer	1	1:2	ECL CML LVDS	ECL	3.3 2.5	1.42	20	0.24	170	3000