MC10SX1189: Fibre Channel Coaxial Cable Driver and Loop Resiliency Circuit

The MC10SX1189 is a differential receiver, differential transmitterspecifically designed to drive coaxial cables. It incorporates the outputcable drive capability of the MC10EL89 Coaxial Cable Driver withadditional circuitry to multiplex the output cable drive source between thecable receiver or the local transmitter inputs. The multiplexer controlcircuitry is TTL compatible for ease of operation. The MC10SX1189 is useful as a bypass element for Fibre Channel-Arbitrated Loop (FC-AL) or Serial Storage Architecture (SSA) applications, to create loop style interconnects with fault tolerant, active switches at each device node. This device is particularly useful for back panel applications where small size is desirable. The EL89 style drive circuitry produces swings twice as large as a standard PECL output. When driving a coaxial cable, proper termination is required at both ends of the line to minimize reflections. The 1.6V output swings allow for proper termination at both ends of the cable, while maintaining the required swing at the receiving end of the cable. Because of the larger output swings, the QT, QTbar outputs are terminated into the thevenin equivalent of 50? to VCC 3.0V instead of 50? to VCC 2.0V.

特性
  • 425ps Propagation Delay
  • 1.6V Output Swing on the Cable Driving Output
  • Single +5V operation
  • 75kW Internal Input Pull-Down Resistors
  • >1000 Volt ESD Protection
  • Pb-Free Packages are Available
封装
应用注释 (12)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Fibre Channel Coaxial Cable Driver and Loop Resiliency CircuitMC10SX1189/D (138kB)5Aug, 2016
仿真模型 (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC10SX1189DMC10SX1189D.IBS (9.0kB)3
封装图纸 (1)
Document TitleDocument ID/SizeRevision
SOIC 16 LEAD751B-05 (38.2kB)K
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC10SX1189DGActivePb-free Halide freeSOIC-16751B-051Tube48联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC10SX1189DGFibre Channel Coaxial Cable Driver12:2ECL2X ECL5150.325 0.65 0.45 0.425400 550
Fibre Channel Coaxial Cable Driver and Loop Resiliency Circuit (138kB) MC10SX1189
AC Characteristics of ECL Devices NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for MC10SX1189D MC10SX1189
SOIC 16 LEAD MC14504B