MC14526B: Presettable 4-Bit Down Counters
The MC14526B binary counter is constructed with MOS P-channel and N-channel enhancement mode devices in a monolithic structure. This device is presettable, cascadable, synchronous down counter with a decoded "0" state output for divide-by-N applications. In single stage applications the "0" output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide-by-N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock. This complementary MOS counter can be used in frequency synthesizers, phase-locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.
特性- Supply Voltage Range = 3.0 Vdc to 18 Vdc
- Logic Edge-Clocked Design - Incremented on Positive Transition of Clock or Negative Transition of Inhibit
- Asynchronous Preset Enable
- Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range
- Pb-Free Packages are Available
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仿真模型 (1)
封装图纸 (1)
| Document Title | Document ID/Size | Revision |
|---|
| SO-16 WB | 751G-03 (56.7kB) | D |
数据表 (1)
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） |
|---|
| MC14526BDWG | Active | Pb-free
Halide free | SOIC-16W | 751G-03 | 3 | Tube | 47 | $0.364 |
| MC14526BDWR2G | Active | Pb-free
Halide free | SOIC-16W | 751G-03 | 3 | Tape and Reel | 1000 | $0.364 |
订购产品技术参数
| Product | Type | VCC Min (V) | VCC Max (V) | tpd Max (ns) | PD Max (W) | IO Max (mA) |
|---|
| MC14526BDWG | Counter | 3 | 18 | 450 | 0.5 | 2.25 |
| MC14526BDWR2G | Counter | 3 | 18 | 450 | 0.5 | 2.25 |
