NB100LVEP56: Multiplexer, 2:1 Differential, Dual ECL, 2.5 V / 3.3 V

The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or differential data signals. The device features both individual and common select inputs to address both data path and random logic applications. Common and individual selects can accept both ECL and CMOS input voltage levels. Multiple VBB pins are provided. The VBB pin, an internally generated voltage supply is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC C via 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

特性

700 ps Typical Propagation Delays
Maximum Frequency > 2.5 GHz Typical
PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = - 2.375 V to - 3.8 V
Separate, Common Select, and Individual Select (Compatible with ECL and CMOS Input Voltage Levels)
Q Output will Default LOW with Inputs Open or at VEE
Multiple VBB Outputs
Pb-Free Packages are Available

封装

应用注释 (14)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit	AN1503/D (120.0kB)	6
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

封装图纸 (2)

Document Title	Document ID/Size	Revision
QFN24, 4x4, 0.5P	485L-01 (60.0kB)	B
TSSOP-20 WB	948E-02 (39.7kB)	D

仿真模型 (3)

Document Title	Document ID/Size	Revision
ECLinPS Plus SPICE Modeling Kit	AND8009 (343.0kB)	11
IBIS Model for NB100LVEP56DT 2.5V	NB100LVEP56DT_25.IBS (6.0kB)	1
IBIS Model for nb100lvep56dt 3.3V	NB100LVEP56DT_33.IBS (5.0kB)	1

评估板文档 (1)

Document Title	Document ID/Size	Revision	Revision Date
Evaluation Board User's Manual for High Frequency TSSOP 20	EVBUM2057/D (247.0kB)	2

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
2.5 V / 3.3 V ECL Dual Differential 2:1 Multiplexer	NB100LVEP56/D (105kB)	11

评估板与开发工具

产品	状况	Compliance	简短说明
ECLTSSOP20EVB	Active		High Frequency TSSOP20 Evaluation Board

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
NB100LVEP56DT	Obsolete	Pb-free	TSSOP-20	948E-02	1	Tube	75
NB100LVEP56DTG	Active	Pb-free Halide free	TSSOP-20	948E-02	1	Tube	75	联系BDTIC
NB100LVEP56DTR2	Obsolete	Pb-free	TSSOP-20	948E-02	1	Tape and Reel	2500
NB100LVEP56DTR2G	Active	Pb-free Halide free	TSSOP-20	948E-02	1	Tape and Reel	2500	联系BDTIC
NB100LVEP56MNG	Active	Pb-free Halide free	QFN-24	485L-01	1	Tube	92	联系BDTIC
NB100LVEP56MNR2G	Active	Pb-free Halide free	QFN-24	485L-01	1	Tape and Reel	3000	联系BDTIC

订购产品技术参数

Product	Input/Output Ratio	Channels	Input Level	Output Level	VCC Typ (V)	fMax Typ (MHz)	tJitter Typ (ps)	tskew(OO) Max (ps)	tpd Typ (ns)
NB100LVEP56DTG	2:1	2	ECL CML LVDS	ECL	3.3 2.5	2500	0.307	50	0.525
NB100LVEP56DTR2G	2:1	2	ECL LVDS CML	ECL	3.3 2.5	2500	0.307	50	0.525
NB100LVEP56MNG	2:1	2	ECL CML LVDS	ECL	3.3 2.5	2500	0.307	50	0.525
NB100LVEP56MNR2G	2:1	2	LVDS CML ECL	ECL	3.3 2.5	2500	0.307	50	0.525