NB100LVEP91: Translator, AnyLevel™ Positive Input to NECL Output Voltage

The NB100LVEP91 is a triple input to NECL output translator. The device accepts LVPECL, LVTTL, HSTL, CML or LVDS signals, and translates them to differential -2.5 V / -3.3 V NECL output signals.To accomplish the level translation, the LVEP91 requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GNDI pins are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01 uF capacitors.Under open input conditions, the Dbar input will be biased at VCC/2 and the D input will be pulled to GND. This condition will force the Q output to a low, ensuring stability.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

特性

Typical Maximum Frequency >2 GHz
430 ps Typical Propagation Delay
Operating Range: VCC = 2.375 V to 3.8 V; VEE = -2.375 V to -3.8 V; GNDI = 0 V
Q Output will default LOW with Inputs Open or at GND
Pb-Free Packages are Available

优势

Design Flexibility

封装

应用注释 (12)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator	NB100LVEP91/D (177kB)	19	Aug, 2016

仿真模型 (4)

Document Title	Document ID/Size	Revision
IBIS Model for NB100LVEP91DW at 2.5V supply	NB100LVEP91DW_25V.IBS (24.0kB)	2
IBIS Model for NB100LVEP91DW at 3.3V supply	NB100LVEP91DW_33V.IBS (24.0kB)	2
IBIS Model for NB100LVEP91MN at 2.5V Supply	NB100LVEP91MN_25.IBS (24.0kB)	5
IBIS Model for NB100LVEP91MN at 3.3 Supply	NB100LVEP91MN_33.IBS (24.0kB)	5

封装图纸 (2)

Document Title	Document ID/Size	Revision
QFN24, 4x4, 0.5P	485L-01 (60.0kB)	B
SOIC-20 WB	751D-05 (36.3kB)	H

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
NB100LVEP91DWG	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tube	38	联系BDTIC
NB100LVEP91DWR2G	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tape and Reel	1000	联系BDTIC
NB100LVEP91MNG	Active	Pb-free Halide free	QFN-24	485L-01	1	Tube	92	联系BDTIC
NB100LVEP91MNR2G	Active	Pb-free Halide free	QFN-24	485L-01	1	Tape and Reel	3000	联系BDTIC

订购产品技术参数

Product	Channels	Input Level	Output Level	VCC Typ (V)	fMax Typ (MHz)	tpd Typ (ns)	tR & tF Max (ps)
NB100LVEP91DWG	3	HSTL CML LVDS	ECL	2.5 3.3	2500	0.5	250
NB100LVEP91DWR2G	3	CML HSTL LVDS	ECL	3.3 2.5	2500	0.5	250
NB100LVEP91MNG	3	HSTL LVDS CML	ECL	3.3 2.5	2500	0.5	250
NB100LVEP91MNR2G	3	HSTL CML LVDS	ECL	3.3 2.5	2500	0.5	250