NB3L202K: 2.5V, 3.3V Differential 1:2 HCSL Fanout Buffer
The NB3L202K is a differential 1:2 Clock fanout buffer with
High−speed Current Steering Logic (HCSL) outputs. Inputs can
directly accept differential LVPECL, LVDS, and HCSL signals.
Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are
accepted with a proper external Vth reference supply per Figures 4
and 6. The input signal will be translated to HCSL and provides two
identical copies operating up to 350 MHz.
The NB3L202K is optimized for ultra−low phase noise, propagation
delay variation and low output–to–output skew, and is DB200H
compliant. As such, system designers can take advantage of the
NB3L202K’s performance to distribute low skew clocks across the
backplane or the motherboard making it ideal for Clock and Data
distribution applications such as PCI Express, FBDIMM, Networking,
Mobile Computing, Gigabit Ethernet, etc.
Output drive current is set by connecting a 475 resistor from
IREF (Pin 10) to GND per Figure 11. Outputs can also interface to
LVDS receivers when terminated per Figure 12.
特性- Maximum Input Clock Frequency > 350 MHz
- 2.5 V ±5% / 3.3 V ±10% Supply Voltage Operation
- 2 HCSL Outputs
- DB200H Compliant
- Individual OE Control Pin for Each Bank of Outputs
- 100 ps Max Output−to−Output Skew Performance
- 1 ns Typical Propagation Delay
- 500 ps Typical Rise and Fall Times
- 80 fs Maximum Additive Phase Jitter RMS
|
应用- Mobile Computing
- Networking
- Gigabit Ethernet
- FBDIMM
- PCI Express
|
应用注释 (5)
封装图纸 (1)
仿真模型 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|
| NB3L202K.IBS | NB3L202K.IBS (53kB) | 0 | |
评估板文档 (1)
数据表 (1)
评估板与开发工具
| 产品 | 状况 | Compliance | 简短说明 |
|---|
| NB3L202KMNGEVB | Active | | 2.5V, 3.3V Differential 1:2 HCSL Fanout Buffer Evaluation Board |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） |
|---|
| NB3L202KMNG | Active | Pb-free
Halide free | QFN-16 | 485AE | 1 | Tube | 123 | 联系BDTIC |
| NB3L202KMNTXG | Active | Pb-free
Halide free | QFN-16 | 485AE | 1 | Tape and Reel | 3000 | 联系BDTIC |
订购产品技术参数
| Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
|---|
| NB3L202KMNG | Buffer | 1 | 1:2 | HCSL
LVDS
LVPECL | HCSL | 3.3
2.5 | 0.046 | 20 | 1 | 700 | 350 | |
| NB3L202KMNTXG | Buffer | 1 | 1:2 | LVDS
HCSL | HCSL | 3.3
2.5 | 0.046 | 20 | 1 | 700 | 350 | |
