NB3L204K: 2.5V, 3.3V Differential 1:4 HCSL Fanout Buffer _ BDTIC 中国领先电子元器件代理商

NB3L204K: 2.5V, 3.3V Differential 1:4 HCSL Fanout Buffer

The NB3L204K is a differential 1:4 Clock fanout buffer with High−speed Current Steering Logic (HCSL) outputs. Inputs can directly accept differential LVPECL, LVDS, and HCSL signals. Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 and 6. The input signal will be translated to HCSL and provides four identical copies operating up to 350 MHz. The NB3L204K is optimized for ultra−low phase noise, propagation delay variation and low output–to–output skew, and is DB400H compliant. As such, system designers can take advantage of the NB3L204K’s performance to distribute low skew clocks across the backplane or the motherboard making it ideal for Clock and Data distribution applications such as PCI Express, FBDIMM, Networking, Mobile Computing, Gigabit Ethernet, etc. Output drive current is set by connecting a 475 resistor from IREF (Pin 14) to GND per Figure 11. Outputs can also interface to LVDS receivers when terminated per Figure 12.

特性

Maximum Input Clock Frequency > 350 MHz
2.5 V ±5% / 3.3 V ±10% Supply Voltage Operation
4 HCSL Outputs
DB400H Compliant
Individual OE Control Pin for Each Bank of Outputs
100 ps Max Output−to−Output Skew Performance
1 ns Typical Propagation Delay
450 ps Typical Rise and Fall Times
80 fs Maximum Additive Phase Jitter RMS

应用

Mobile Computing
Networking
Gigabit Ethernet
FBDIMM
PCI Express

应用注释 (5)

Document Title	Document ID/Size	Revision	Revision Date
Board Level Application Notes for DFN and QFN Packages	AND8211/D (175.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Semiconductor Package Thermal Characterization	AND8215/D (363.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016