NB3N853501E: Input Mux - 2:1, LVTTL / LVCMOS, 3.3 V, Fanout Buffer - 1:4 LVPECL
The NB3N853501E is a low skew 3.3 V supply 2:1:4 clock distribution fanout buffer. An Input MUX selects one of two LVCMOS/LVTTL CLK lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using LVCMOS/LVTTL levels. A CLK_EN pin can enable or disable the outputs synchronously to eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable outputs, LOW to disable output).
特性- Four differential LVPECL Outputs
- Operating range: VCC = 3.3 5% V( 3.135 to 3.465 V)
- Two Selectable LVCMOS/LVTTL CLOCK Inputs
- Up to 266 MHz Clock Operation
- Output to Output Skew: 30 ps
- Device to Device Skew 250 ps (Max.)
- Propagation Delay 1.9 ns (Max.)
- Additive Phase Jitter, RMS: 0.023 ps (Typ)
- Industrial Temp. Range (40C to 85C)
| 优势- Multiple copies of the Clock
- Ensures operation in the majority of designs
|
应用- Teleconmmunications
- Networking
- Computing Systems
- SONET/SDH
| 终端产品- LAN/WAN
- Enterprise Servers
- ATE
- Test and Measurement
|
应用注释 (8)
封装图纸 (1)
| Document Title | Document ID/Size | Revision |
|---|
| TSSOP-20 WB | 948E-02 (39.7kB) | D |
数据表 (1)
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） |
|---|
| NB3N853501EDTG | Active | Pb-free
Halide free | TSSOP-20 | 948E-02 | 1 | Tube | 75 | 联系BDTIC |
| NB3N853501EDTR2G | Active | Pb-free
Halide free | TSSOP-20 | 948E-02 | 1 | Tape and Reel | 2500 | 联系BDTIC |
订购产品技术参数
| Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
|---|
| NB3N853501EDTG | Buffer | 1 | 2:1:4 | LVCMOS
LVTTL | LVPECL | 3.3 | 0.062 | 30 | | 700 | 266 | |
| NB3N853501EDTR2G | Buffer | 1 | 2:1:4 | LVTTL
LVCMOS | LVPECL | 3.3 | 0.062 | 30 | | 700 | 266 | |
