NB4L339: 2.5 V / 3.3 V Clock Distribution IC for SONET/SDH

The NB4L339 is a multi-function Clock generator featuring a 2:1 Clock multiplexer front end and simultaneously outputs a selection of four different divide ratios from its four divider blocks; div1, div2, div4 and div8. One divide block has a choice of div1 or div2. The output of each divider block is fanned-out to two identical differential LVPECL copies of the selected clock. All outputs provide standard LVPECL voltage levels when externally terminated with a 50-ohm resistor to VCC - 2 V. The differential Clock inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, CML or LVDS logic levels. The common Output Enable pin (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock. Therefore, all associated specification limits are referenced to the negative edge of the clock input. This device is housed in a 5x5 mm 32 pin QFN package.

特性
  • 0.5 ps Typical RMS Random Clock Period Jitter
  • LVPECL, CML or LVDS Input Compatible
  • 0.15 ps Typical RMS Phase Jitter
  • Low Skew LVPECL Outputs, 15 ps typical
优势
  • Very Low Jitter Clock Output
  • Multi Level Input Interface
应用
  • Clock Generation for SONET applications
应用注释 (3)
Document TitleDocument ID/SizeRevisionRevision Date
Interfacing with ECLinPSAND8066/D (72kB)3
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
封装图纸 (1)
Document TitleDocument ID/SizeRevision
QFN32, 5x5, 0.5P, 3.1x3.1EP488AM (57.4kB)A
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5 V / 3.3 V Differential 2:1 Clock In to Differential LVPECL Clock Generator / Divider / Fan−Out BufferNB4L339/D (138.0kB)3
评估板文档 (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB4L339MNGEVB Evaluation Board User's ManualEVBUM2070/D (183.0kB)1
评估板与开发工具
产品状况Compliance简短说明
NB4L339MNGEVBActivePb-freeSONET/SDH Clock Distribution IC Evaluation Board
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
NB4L339MNGActivePb-free Halide freeQFN-32488AM1Tube74联系BDTIC
NB4L339MNR4GActivePb-free Halide freeQFN-32488AM1Tape and Reel1000联系BDTIC
订购产品技术参数
ProductTypeInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
NB4L339MNGDividerCML LVDS ECLECL2.5 3.37001.3250
NB4L339MNR4GDividerCML ECL LVDSECL2.5 3.37001.3250
2.5 V / 3.3 V Differential 2:1 Clock In to Differential LVPECL Clock Generator / Divider / Fan−Out Buffer (138.0kB) NB4L339
Interfacing with ECLinPS NB100LVEP91
Termination of ECL Logic Devices NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
EVBUM2070/D - 183 NB4L339MNGEVB
QFN32, 5x5, 0.5P, 3.1x3.1EP NCN6804