NB7L32M: ÷·2 Divider with CML Output
The NB7L32M is an integrated /2 divider with differential clock inputs and asynchronous reset.Differential clock inputs incorporate internal 50 Ω termination resistors and accept LVPECL (Positive ECL), CML, or LVDS. The high frequency reset pin is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple NB7L32M's in a system.The differential 16 mA CML output provides matching internal 50 Ω termination which guarantees 400 mV output swing when externally receiver terminated 50 Ω to VCC (See Figure 16).The device is housed in a small 3x3 mm 16 pin QFN package.
特性- Maximum Input Clock Frequency 14 GHz Typical
- 200 ps Max Propagation Delay
- 30 ps Typical Rise and Fall Times
- < 0.5 ps Maximum (RMS) Random Clock Jitter
- Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
- CML Output Level (400 mV Peak-to-Peak Output), Differential Output Only
- 50 Ω Internal Input and Output Termination Resistors
- Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices
- Full RoHS Compliance.
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应用- High frequency clock division in Automated Test Equipment.
- Ultra precise clock division in networking and telecomm applications.
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应用注释 (5)
封装图纸 (1)
仿真模型 (1)
评估板文档 (1)
数据表 (1)
评估板与开发工具
| 产品 | 状况 | Compliance | 简短说明 |
|---|
| NB7L32MMNGEVB | Active | Pb-free | 2.5V / 3.3V 12 GHz Divide by 2 with CML Output Evaluation Board |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） |
|---|
| NB7L32MMNG | Active | Pb-free
Halide free | QFN-16 | 485G-01 | 1 | Tube | 123 | 联系BDTIC |
| NB7L32MMNR2G | Active | Pb-free
Halide free | QFN-16 | 485G-01 | 1 | Tape and Reel | 3000 | 联系BDTIC |
订购产品技术参数
| Product | Type | Input Level | Output Level | VCC Typ (V) | fMax Typ (MHz) | tpd Typ (ns) | tR & tF Max (ps) |
|---|
| NB7L32MMNG | Divider | CML
ECL
LVDS | CML | 2.5
3.3 | 14000 | 0.155 | 45 |
| NB7L32MMNR2G | Divider | ECL
LVDS
CML | CML | 3.3
2.5 | 14000 | 0.155 | 45 |
