NB7N017M: 8-bit Divider with CML Output

The NB7N017M is a high speed 8 bit dual modulus programmable divider/prescaler with 16 mA CML outputs capable of switching at input frequencies greater than 3.5 GHz. The CML output structure contains internal 50 ohm source termination resistor to VCC. The device generates 400 mV output amplitude with 50 ohm receiver resistor to VCC. This I/O structure enables easy implementation of the NB7N017M in 50 ohm systems. The differential inputs contain 50 ohm termination resistors to VT pads and all differential inputs accept RSECL, ECL, LVDS, LVCMOS, LVTTL, and CML. Internally, the NB7N017M uses a greater than 3.5 GHz 8 bit programmable down counter. A select pin, SEL, is used to select between two words, Pa(0:7) and Pb(0:7), that are stored in REGa and REGb respectively. Two parallel load pins, PLa and PLb, are used to load the level triggered programming registers, REGa and REGb,respectively. A differential clock enable, CE, pin is available. The NB7N017M offers a differential output, TC. Terminal count output, TC, goes high for one clock cycle when the counter has reached the all zeros state. To reduce output phase noise, TC is retimed with the rising edge triggered latches.

特性
  • Maximum Input Clock Frequency > 3.5 GHz Typical
  • 50 ohm Internal Input and Output Termination Resistors
  • All SingleEnded Control Pins CMOS and PECL/NECL Compatible
  • Counter Programmed Using One of Two Single-Ended Words,Pa and Pb, Stored in REGa and REGb
  • CML Output Level: 400 mV PeakPeak Output with 50 ohm Receiver Resistor to VCC
  • 16 mA CML output with 50 ohm Internal Source Terminationto VCC
  • Differential CLK, CE, and SEL Input
  • Compatible with Existing 3.3 V LVEP, EP, and SG Devices
  • PbFree Packages are Available
应用
  • PLL
  • Divider
应用注释 (13)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output StructureAND8173/D (144.0kB)3
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
封装图纸 (1)
Document TitleDocument ID/SizeRevision
8X8MM 0.5MM PITCH485M (60.8kB)C
仿真模型 (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for nb7n017m 3.3VNB7N017M.IBS (23.0kB)3
评估板文档 (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB7N017M Evaluation Board User's ManualEVBUM2088/D (165.0kB)2
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V SiGe 8-Bit Dual Modulus Programmable Divider/Prescaler with CML OutputsNB7N017M/D (200kB)5Aug, 2016
评估板与开发工具
产品状况Compliance简短说明
NB7N017MEVBActiveDual Modulus Programmable Divider/Prescaler Evaluation Board
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
NB7N017MMNGActivePb-free Halide freeQFN-52485M2Tray JEDEC260联系BDTIC
NB7N017MMNR2GActivePb-free Halide freeQFN-52485M2Tape and Reel2000联系BDTIC
订购产品技术参数
ProductTypeInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
NB7N017MMNGDividerLVDS ECL CML LVCMOSCML3.335000.51565
NB7N017MMNR2GDividerCML ECL LVCMOS LVDSCML3.335000.51565
3.3 V SiGe 8-Bit Dual Modulus Programmable Divider/Prescaler with CML Outputs (200kB) NB7N017M
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output Structure NB6L295M
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for nb7n017m 3.3V NB7N017M
EVBUM2088/D - 165 NB7N017MEVB
8X8MM 0.5MM PITCH NB4L7210