NB7V33MMNGEVB: Differential Clock Divider Evaluation Border
The NB7V33M is a differential divide by 4 Clock divider with asynchronous reset. The differential Clock inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, CML and LVDS logic levels. The NB7V33M produces a div 4 output copy of an input Clock operating up to 10GHz with minimal jitter. The Reset pin is asserted on the rising edge. Upon powerup, the internal flip-flops will attain a random state. The Reset allows for the synchronization of multiple NB7V33Ms in a system. The 16mA differential CML output provides matching internal 50-ohm termination which provides 400mV output swing when externally receiver terminated with 50-ohm to VCC.
评估/开发工具信息
| 产品 | 状况 | Compliance | 简短说明 | 所用产品 |
|---|
| NB7V33MMNGEVB | Active | Pb-free | Differential Clock Divider Evaluation Border | NB7V33MMNG |
技术文档
