/**
  @page TIM9_ETR_LSE TIM9 LSE ETR example
  
  @verbatim
  ******************** (C) COPYRIGHT 2012 STMicroelectronics *******************
  * @file    TIM/TIM9_ETR_LSE/readme.txt 
  * @author  MCD Application Team
  * @version V1.1.1
  * @date    13-April-2012
  * @brief   Description of the TIM9 LSE ETR example.
  ******************************************************************************
  *
  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  * You may not use this file except in compliance with the License.
  * You may obtain a copy of the License at:
  *
  *        http://www.st.com/software_license_agreement_liberty_v2
  *
  * Unless required by applicable law or agreed to in writing, software 
  * distributed under the License is distributed on an "AS IS" BASIS, 
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  *
  ******************************************************************************
   @endverbatim

@par Example Description 


This example explains how to configure TIM9 time base that works completely 
independently of the system clock. This allows the scheduling of tasks without
having to take into account the processor state (the processor may be stopped 
or executing at low, medium or full speed).
For this purpose, the LSE clock is internally redirected to the TIM9 ETR input.

Moreover, this example shows how to configure the TIM9 channel 1 in PWM 
(Pulse Width Modulation) mode and to be clocked with the LSE clock.
The TIMxCLK frequency is set to the LSE frequency 32.768 KHz, the Prescaler is 0
so the TIM9 counter clock is 32.768 KHz.

The TIM9 ARR register value is equal to 0x1F, so an update event is generated
each (0x1F + 1) / 32.768KHz ~ 1 ms

The TIM9 ARR register value is equal to 0x1F, so the TIM9 Channel 1 generates a 
PWM signal with a frequency equal to 1KHz

The TIM9 CCR1 register value is equal to 0x8, so the TIM9 Channel 1 generates a 
PWM signal with a duty cycle equal to 25%:
TIM9 Channel1 duty cycle = (TIM9_CCR1/ TIM9_ARR + 1)* 100 = 25%

The PWM waveform can be displayed using an oscilloscope.

@par Directory contents 

  - TIM/TIM9_ETR_LSE/stm32l1xx_conf.h     Library Configuration file
  - TIM/TIM9_ETR_LSE/stm32l1xx_it.c       Interrupt handlers
  - TIM/TIM9_ETR_LSE/stm32l1xx_it.h       Header for stm32l1xx_it.c
  - TIM/TIM9_ETR_LSE/main.c               Main program
  - TIM/TIM9_ETR_LSE/system_stm32l1xx.c   STM32L1xx system source file
  
@note The "system_stm32l1xx.c" is generated by an automatic clock configuration 
      system and can be easily customized to your own configuration. 
      To select different clock setup, use the "STM32L1xx_Clock_Configuration_V1.1.0.xls" 
      provided with the AN3309 package available on <a href="http://www.st.com/internet/mcu/family/141.jsp">  ST Microcontrollers </a>
         
@par Hardware and Software environment

  - This example runs on STM32L1xx Ultra Low Power High-, Medium-Density and Medium-Density Plus Devices.
  
  - This example has been tested with STMicroelectronics STM32L152D-EVAL (STM32L1xx 
    Ultra Low Power High-Density) and STM32L152-EVAL (STM32L1xx Ultra Low 
    Power Medium-Density) evaluation board and can be easily tailored to any 
    other supported device and development board.

  - STM32L152-EVAL and STM32L152D-EVAL Set-up
    - Connect the PA.02 pin to the scope.

@par How to use it ? 

In order to make the program work, you must do the following :
 - Copy all source files from this example folder to the template folder under
   Project\STM32L1xx_StdPeriph_Templates
 - Open your preferred toolchain 
 - Rebuild all files and load your image into target memory
 - Run the example

@note
- Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx 
  microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and 
  STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes.
- Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx 
  microcontrollers where the Flash memory density is 384 Kbytes.

 * <h3><center>&copy; COPYRIGHT STMicroelectronics</center></h3>
 */


