/**
  @page TIM_OCInactive TIM OC Inactive example
  
  @verbatim
  ******************** (C) COPYRIGHT 2012 STMicroelectronics *******************
  * @file    TIM/OCInactive/readme.txt 
  * @author  MCD Application Team
  * @version V1.1.1
  * @date    13-April-2012
  * @brief   Description of the TIM OC Inactive example.
  ******************************************************************************
  *
  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  * You may not use this file except in compliance with the License.
  * You may obtain a copy of the License at:
  *
  *        http://www.st.com/software_license_agreement_liberty_v2
  *
  * Unless required by applicable law or agreed to in writing, software 
  * distributed under the License is distributed on an "AS IS" BASIS, 
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  *
  ******************************************************************************
   @endverbatim

@par Example Description 

This example shows how to configure the TIM peripheral in Output Compare Inactive 
mode with the corresponding Interrupt requests for each channel.

The TIM3CLK frequency is set to SystemCoreClock , and the objective is
to get TIM3 counter clock at 1 KHz so the Prescaler is computed as following:
   - Prescaler = (TIM3CLK / TIM3 counter clock) - 1
SystemCoreClock is set to 32 MHz for Ultra Low Power Medium-Density and High-Density
Devices.

The TIM3 CCR1 register value is equal to 1000:
TIM3_CC1 delay = CCR1_Val/TIM3 counter clock  = 1000 ms
so the PD.00  is reset after a delay equal to 1000 ms.

The TIM3 CCR2 register value is equal to 500:
TIM3_CC2 delay = CCR2_Val/TIM3 counter clock = 500 ms
so the PD.01  is reset after a delay equal to 500 ms.

The TIM3 CCR3 register value is equal to 250:
TIM3_CC3 delay = CCR3_Val/TIM3 counter clock = 250 ms
so the PD.04  is reset after a delay equal to 250 ms.

The TIM3 CCR4 register value is equal to 125:
TIM3_CC4 delay = CCR4_Val/TIM2 counter clock = 125 ms
so the PD.05  is reset after a delay equal to 125 ms.

While the counter is lower than the Output compare registers values, which 
determines the Output delay, the PD.00, PD.01, PD.04 and PD.05 pin are turned on. 

When the counter value reaches the Output compare registers values, the Output 
Compare interrupts are generated and, in the handler routine, these pins are turned off.


@par Directory contents 

  - TIM/OCInactive/stm32l1xx_conf.h    Library Configuration file
  - TIM/OCInactive/stm32l1xx_it.c      Interrupt handlers
  - TIM/OCInactive/stm32l1xx_it.h      Interrupt handlers header file
  - TIM/OCInactive/main.c              Main program
  - TIM/OCInactive/system_stm32l1xx.c  STM32L1xx system source file
  
@note The "system_stm32l1xx.c" is generated by an automatic clock configuration 
      system and can be easily customized to your own configuration. 
      To select different clock setup, use the "STM32L1xx_Clock_Configuration_V1.1.0.xls" 
      provided with the AN3309 package available on <a href="http://www.st.com/internet/mcu/family/141.jsp">  ST Microcontrollers </a>
         
@par Hardware and Software environment

  - This example runs on STM32L1xx Ultra Low Power High-, Medium-Density and Medium-Density Plus Devices.
  
  - This example has been tested with STMicroelectronics STM32L152D-EVAL (STM32L1xx 
    Ultra Low Power High-Density) and STM32L152-EVAL (STM32L1xx Ultra Low 
    Power Medium-Density) evaluation board and can be easily tailored to any 
    other supported device and development board.

  - STM32L152-EVAL and STM32L152D-EVAL Set-up 
    - Connect the following pins to an oscilloscope to monitor the different 
      waveforms:
        - TIM3 CH1 (PD.00) 
        - TIM3 CH2 (PD.01)
        - TIM3 CH1 (PD.04) 
        - TIM3 CH2 (PD.05) 
  
@par How to use it ? 

In order to make the program work, you must do the following :
 - Copy all source files from this example folder to the template folder under
   Project\STM32L1xx_StdPeriph_Templates
 - Open your preferred toolchain 
 - Rebuild all files and load your image into target memory
 - Run the example

@note
- Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx 
  microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and 
  STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes.
- Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx 
  microcontrollers where the Flash memory density is 384 Kbytes.  
   
 * <h3><center>&copy; COPYRIGHT STMicroelectronics</center></h3>
 */


