/**
  @page TIM_TimeBase TIM Time Base example
  
  @verbatim
  ******************** (C) COPYRIGHT 2012 STMicroelectronics *******************
  * @file    TIM/TimeBase/readme.txt 
  * @author  MCD Application Team
  * @version V1.1.1
  * @date    13-April-2012
  * @brief   Description of the TIM Time Base example.
  ******************************************************************************
  *
  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  * You may not use this file except in compliance with the License.
  * You may obtain a copy of the License at:
  *
  *        http://www.st.com/software_license_agreement_liberty_v2
  *
  * Unless required by applicable law or agreed to in writing, software 
  * distributed under the License is distributed on an "AS IS" BASIS, 
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  *
  ******************************************************************************
   @endverbatim

@par Example Description 

This example shows how to configure the TIM peripheral in Output Compare Timing 
mode with the corresponding Interrupt requests for each channel in order to generate
4 different time bases.

The TIM2CLK frequency is set to SystemCoreClock, TIM2 prescaler is set to 0.
SystemCoreClock is set to 32 MHz for Ultra Low Power Medium-Density and High-Density
Devices.

The TIM2 CC1 register value is equal to 40961, 
CC1 update rate = TIM2 counter clock / CCR1_Val = 781 Hz,
so the TIM2 Channel 1 generates an interrupt each 1.28 ms

The TIM2 CC2 register is equal to 27309, 
CC2 update rate = TIM2 counter clock / CCR2_Val = 1.17 KHz
so the TIM2 Channel 2 generates an interrupt each 0.85 ms

The TIM2 CC3 register is equal to 13654, 
CC3 update rate = TIM2 counter clock / CCR3_Val = 2.34 KHz
so the TIM2 Channel 3 generates an interrupt each 0.42 ms

The TIM2 CC4 register is equal to 6826, 
CC4 update rate = TIM2 counter clock / CCR4_Val =  4.68 KHz
so the TIM2 Channel 4 generates an interrupt each 0.21 ms.

When the counter value reaches the Output compare registers values, the Output 
Compare interrupts are generated and, in the handler routine, 4 pins(PC.00, PC.01,
PC.02 and  PC.03) are toggled with the following frequencies: 

- PC.00: 390 Hz   (CC1)
- PC.01: 585 Hz   (CC2)
- PC.02: 1.17 KHz (CC3) 
- PC.03: 2.34 KHz (CC4)

@par Directory contents 

  - TIM/TimeBase/stm32l1xx_conf.h    Library Configuration file
  - TIM/TimeBase/stm32l1xx_it.c      Interrupt handlers
  - TIM/TimeBase/stm32l1xx_it.h      Interrupt handlers header file
  - TIM/TimeBase/main.c              Main program 
  - TIM/TimeBase/system_stm32l1xx.c  STM32L1xx system source file
  
@note The "system_stm32l1xx.c" is generated by an automatic clock configuration 
      system and can be easily customized to your own configuration. 
      To select different clock setup, use the "STM32L1xx_Clock_Configuration_V1.1.0.xls" 
      provided with the AN3309 package available on <a href="http://www.st.com/internet/mcu/family/141.jsp">  ST Microcontrollers </a>
         
@par Hardware and Software environment


  - This example runs on STM32L1xx Ultra Low Power High-, Medium-Density and Medium-Density Plus Devices.
  
  - This example has been tested with STMicroelectronics STM32L152D-EVAL (STM32L1xx 
    Ultra Low Power High-Density) and STM32L152-EVAL (STM32L1xx Ultra Low 
    Power Medium-Density) evaluation board and can be easily tailored to any 
    other supported device and development board.

  - STM32L152-EVAL and STM32L152D-EVAL Set-up 
    - Connect an oscilloscope on PC.00, PC.01, PC.02 and PC.03 to display the 
      different Time Base signals.  
  
@par How to use it ? 

In order to make the program work, you must do the following :
 - Copy all source files from this example folder to the template folder under
   Project\STM32L1xx_StdPeriph_Templates
 - Open your preferred toolchain 
 - Rebuild all files and load your image into target memory
 - Run the example

@note
- Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx 
  microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and 
  STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes.
- Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx 
  microcontrollers where the Flash memory density is 384 Kbytes.  
   
 * <h3><center>&copy; COPYRIGHT STMicroelectronics</center></h3>
 */



