AD5378 32-Channel 14-Bit Serial/Parallel Bipolar D/A Converter

The AD5378 guarantees operation over a wide VSS/VDD supply range from ±11.4 V to ±16.5 V. The output amplifier headroom requirement is 2.5 V operating with a load current of 1.5 mA, and 2 V operating with a load current of 0.5 mA. The AD5378 contains a double-buffered parallel interface in which 14 data bits are loaded into one of the input registers under the control of the WR, CS, and DAC channel address pins, A0 to A7. It also has a 3-wire serial interface, which is compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz. The DAC outputs are updated when the DAC registers receive new data. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register. Each DAC output is gained and buffered on-chip with respect to an external REFGND input. The DAC outputs can also be switched to REFGND via the CLR pin. Table 1 and Table 2 show the product portfolio for high channel count bipolar and unipolar voltage output DACs. Applications Level setting in automatic test equipment (ATE) Variable optical attenuators (VOAs) Optical switches Industrial control systems

The AD5378 contains 32 14-bit DACs in one CSPBGA package. The AD5378 provides a bipolar output range determined by the voltages applied to the VREF(+) and VREF(−) inputs. The maximum output voltage span is 17.5 V, corresponding to a bipolar output range of −8.75 V to +8.75 V, and is achieved with reference voltages of VREF(−) = −3.5 V and VREF(+) = +5 V.

The AD5378 contains a double-buffered parallel interface in which 14 data bits are loaded into one of the input registers under the control of the WR, CS, and DAC channel address pins, A0 to A7. It also has a 3-wire serial interface, which is compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz.

The DAC outputs are updated when the DAC registers receive new data. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register.

Each DAC output is gained and buffered on-chip with respect to an external REFGND input. The DAC outputs can also be switched to REFGND via the CLR pin. Table 1 and Table 2 show the product portfolio for high channel count bipolar and unipolar voltage output DACs.