The AD7721 can be operated with input bandwidths up to 229.2 kHz. The corresponding output word rate is 468.75 kHz. The part can be operated with lower clock frequencies also. The sample rate, filter corner frequency, settling time, group delay and output word rate will be reduced also, as these are proportional to the external clock frequency. The maximum clock frequencies in parallel mode and serial mode are 10 MHz and 15 MHz respectively. Use of a single bit DAC in the modulator guarantees excellent linearity and dc accuracy. Endpoint accuracy is ensured by on-chip calibration of offset and gain. This calibration procedure minimizes the part’s zero-scale and full-scale errors. The output data is accessed from the output register through a serial or parallel port. This offers easy, high speed interfacing to modern microcontrollers and digital signal processors. The serial interface operates in internal clocking (master) mode, the AD7721 providing the serial clock. CMOS construction ensures low power dissipation while a power-down mode reduces the power consumption to only 100 µW.
The AD7721 is a complete low power, 12-/16-bit, sigma-delta ADC. The part operates from a +5 V supply and accepts a differential input of 0 V to 2.5 V or ±1.25 V. The analog input is continuously sampled by an analog modulator at twice the clock frequency eliminating the need for external sample-and-hold circuitry. The modulator output is processed by two finite impulse response (FIR) digital filters in series. The on-chip filtering reduces the external antialias requirements to first order in most cases. Settling time for a step input is 218.4 µs while the group delay for the filter is 109.2 µs when the master clock equals 15 MHz.
The AD7721 can be operated with input bandwidths up to 229.2 kHz. The corresponding output word rate is 468.75 kHz. The part can be operated with lower clock frequencies also. The sample rate, filter corner frequency, settling time, group delay and output word rate will be reduced also, as these are proportional to the external clock frequency. The maximum clock frequencies in parallel mode and serial mode are 10 MHz and 15 MHz respectively.
Use of a single bit DAC in the modulator guarantees excellent linearity and dc accuracy. Endpoint accuracy is ensured by on-chip calibration of offset and gain. This calibration procedure minimizes the part’s zero-scale and full-scale errors.
The output data is accessed from the output register through a serial or parallel port. This offers easy, high speed interfacing to modern microcontrollers and digital signal processors. The serial interface operates in internal clocking (master) mode, the AD7721 providing the serial clock.
CMOS construction ensures low power dissipation while a power-down mode reduces the power consumption to only 100 µW.
Features and Benefits
| Analog to Digital Converters |
| Document | note |
| AD7721: CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC Data Sheet (Rev. A) | PDF 259 kB |
| Part Number | Package | Packing Qty | Temp Range | Price 100-499 | Price 1000+ | RoHS |
|---|---|---|---|---|---|---|
| AD7721AR Production | 28 ld SOIC - Wide | OTH 27 | -40 to 85C | 0 | 0 | N |
| AD7721ARZ Production | 28 ld SOIC - Wide | OTH 27 | -40 to 85C | 15.51 | 13.02 | Y |
| AD7721ARZ-REEL Production | 28 ld SOIC - Wide | REEL 1000 | -40 to 85C | 0 | 13.02 | Y |
