AD9259 Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC

The AD9259 is a quad, 14-bit, 50 MSPS analog-to-digital con- verter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 50 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. Small Footprint. Four ADCs are contained in a small, space-saving package. Low power of 98 mW/channel at 50 MSPS. Ease of Use. A data clock output (DCO) operates at frequencies of up to 350 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9219 (10-bit), and AD9228 (12-bit).

The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI).

The AD9259 is available in a RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C.

Product Highlights
  • Small Footprint. Four ADCs are contained in a small, space-saving package.
  • Low power of 98 mW/channel at 50 MSPS.
  • Ease of Use. A data clock output (DCO) operates at frequencies of up to 350 MHz and supports double data rate (DDR) operation.
  • User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements.
  • Pin-Compatible Family. This includes the AD9287 (8-bit), AD9219 (10-bit), and AD9228 (12-bit).

Applications
  • Medical imaging and nondestructive ultrasound
  • Portable ultrasound and digital beam-forming systems
  • Quadrature radio receivers
  • Diversity radio receivers
  • Tape drives
  • Optical networking
  • Test equipment
Features and Benefits
  • 4 ADCs integrated into 1 package
  • 98 mW ADC power per channel at 50 MSPS
  • SNR = 73 dB (to Nyquist)
  • ENOB = 12 bits
  • SFDR = 84 dBc (to Nyquist)
  • Excellent linearity
  • DNL = ±0.5 LSB (typical)
  • INL = ±1.5 LSB (typical)
  • Serial LVDS (ANSI-644, default)
  • Low power, reduced signal option (similar to IEEE 1596.3)
  • Data and frame clock outputs
  • 315 MHz full-power analog bandwidth
  • 2 V p-p input voltage range
  • 1.8 V supply operation
  • Please refer to the data sheet for more information
Analog to Digital Converters
AD9259 IBIS Models
Data Sheets
Documentnote
AD9259: Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC Data Sheet (Rev. E)PDF 1873 kB
Application Notes
Documentnote
AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual (Rev. 0)PDF 2124 kB
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)PDF 985 kB
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)PDF 227 kB
AN-282: Fundamentals of Sampled Data SystemsPDF 2131 kB
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)PDF 291.7 K
AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev. 0)PDF 203 kB
AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0)PDF 363 kB
AN-742: Frequency Domain Response of Switched-Capacitor ADCs (Rev. B)PDF 401 kB
AN-345: Grounding for Low-and-High-Frequency CircuitsPDF 455 kB
AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0)PDF 392 kB
AN-737: How ADIsimADC Models an ADC (Rev. B)PDF 373 kB
AN-807: Multicarrier WCDMA Feasibility (Rev. 0)PDF 969 kB
AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0)PDF 1535 kB
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit (Rev. 0)
Software Download (zip, 21,702,560 bytes)
PDF 441 kB
AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated (Rev. 0)PDF 370.2 K
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)PDF 1679 kB
Order Information
Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
AD9259ABCPZ-50 Production48 ld LFCSP (7x7x.85 w/5.5mm EP)OTH 260-40 to 85C53.5445.54Y
AD9259ABCPZRL7-50 Production48 ld LFCSP (7x7x.85 w/5.5mm EP)REEL 750-40 to 85C53.5445.54Y
Evaluation Boards
Part NumberDescriptionPriceRoHS
AD9259-50EBZEvaluation Board202.4Y
Reference Materials
AD9259: Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC Data Sheet (Rev. E) ad9259
AD9259BCP (All Speeds) ad9259
AN-808: CDMA2000多载波系统可行性研究 (Rev. 0) adl5330
AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual (Rev. 0) ad9220
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B) ad9220
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A) ad9220
AN-282: Fundamentals of Sampled Data Systems ad1674
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0) ad9220
AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev. 0) ad6655
AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0) ad9220
AN-742: Frequency Domain Response of Switched-Capacitor ADCs (Rev. B) ad7476
AN-345: Grounding for Low-and-High-Frequency Circuits ad9220
AN-835: 高速ADC测试和评估 (Rev. 0) ad9510
AN-1142: 高速ADC PCB布局布线技巧 (Rev. 0) ad6655
AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0) ad6655
AN-282: 采样数据系统基本原理[中文版] (Rev. A) ad75019
AN-737: 如何用ADIsimADC完成ADC建模 (Rev. B) ad6642
AN-737: How ADIsimADC Models an ADC (Rev. B) ad9220
AN-807: 多载波WCDMA的可行性 (Rev. 0) adf4106
AN-807: Multicarrier WCDMA Feasibility (Rev. 0) ad6655
AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0) ad9863
AN-827: 放大器与开关电容ADC接口的匹配方法[中文版] (Rev. 0) ad8351
AN-905: VisualAnalog™转换器评估工具1.0版用户手册 (Rev. 0) ad6655
AN-935: ADC变压器耦合前端设计[中文版] (Rev. 0) ad6655
AN-812: 基于微控制器的串行端口接口(SPI®)启动电路 (Rev. 0) adg3304
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit (Rev. 0) ad6655
Software Download (zip, 21,702,560 bytes) ad6655
AN-715: 走近IBIS模型:什么是IBIS模型?它们是如何生成的? (Rev. 0) ad6655
AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated (Rev. 0) ad9220
AN-345: 低频和高频电路接地 ad9540
AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版] (Rev. 0) ad9540
AN-501: 孔径不确定度与ADC系统性能[中文版] (Rev. A) ad9540
AN-741: Little Known Characteristics of Phase Noise (Rev. 0) ad9221
AN-741: 鲜为人知的相位噪声特性 ad9540
MS-2210:高速ADC的电源设计 ad9861