AD9433 12-Bit 105/125 MSPS Analog-To-Digital IF Sampling Converter

A user-selectable, on-chip proprietary circuit optimizes spurious-free dynamic range (SFDR) versus signal-to-noise-and-distortion (SINAD) ratio performance for different input signal frequencies, providing as much as 83 dBc SFDR performance over the dc to 70 MHz band. The encode clock supports either differential or single-ended input and is PECL-compatible. The output format is user-selectable for binary or two's complement and provides an overrange (OR) signal. Fabricated on an advanced BiCMOS process, the AD9433 is available in a 52-lead thin quad flat package (TQFP_EP) that is specified over the industrial temperature range of −40°C to +85°C. The AD9433 is pin-compatible with the AD9432.

The AD9433 is a 12-bit monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and is designed for ease of use. The product operates up to 125 Msps conversion rate and is optimized for outstanding dynamic performance in wideband and high IF carrier systems.

The ADC requires a +5V analog power supply and a differential encode clock for full performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3V or 2.5V logic.

The encode clock supports either differential or single-ended input and is PECL-compatible. The output format is user-selectable for binary or two's complement and provides an overrange (OR) signal.

Fabricated on an advanced BiCMOS process, the AD9433 is available in a 52-lead thin quad flat package (TQFP_EP) that is specified over the industrial temperature range of −40°C to +85°C. The AD9433 is pin-compatible with the AD9432.

Features and Benefits

IF Sampling up to 350 MHz
SNR: 67.5 dB, fin up to Nyquist at 105 MSPS
SFDR: 83 dBc, fin = 70 MHz at 105 MSPS
SFDR = 72 dBc, fin = 150 MHz at 105 MSPS
2 Vp-p analog input range
On-chip clock duty cycle stabilization
On-chip reference and track-and-hold

SFDR Optimization Circuit
Excellent Linearity
DNL = ± 0.25 LSB (Typ)
INL = ± 0.5 LSB (Typ)
750 MHz full power analog bandwidth
Power Dissipation = 1.35W at 125 MSPS
Twos complement or offset binary data format
See data sheet for additional features

Analog to Digital Converters

AD9433 IBIS Models

AD9433BSQ (All Speed Grades) .IBS

Data Sheets

Document	note
AD9433: 12-Bit, 105 MSPS/125 MSPS, IF Sampling ADC Data Sheet (Rev. A)	PDF 989 kB

Application Notes

Document	note
AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual (Rev. 0)	PDF 2124 kB
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)	PDF 985 kB
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)	PDF 227 kB
AN-282: Fundamentals of Sampled Data Systems	PDF 2131 kB
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)	PDF 291.7 K
AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0)	PDF 363 kB
AN-345: Grounding for Low-and-High-Frequency Circuits	PDF 455 kB
AN-737: How ADIsimADC Models an ADC (Rev. B)	PDF 373 kB
AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0)	PDF 1535 kB
AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated (Rev. 0)	PDF 370.2 K
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)	PDF 1679 kB

Order Information

Part Number	Package	Packing Qty	Temp Range	Price 100-499	Price 1000+	RoHS
AD9433BSVZ-105 Production	52 ld TQFP_EP(10x10 w/7.3 ep)	OTH 160	-40 to 85C	38.65	32.84	Y
AD9433BSVZ-125 Production	52 ld TQFP_EP(10x10 w/7.3 ep)	OTH 160	-40 to 85C	40.61	34.51	Y