AD9518-0 6-Output Clock Generator with Integrated 2.8 GHz VCO

The AD9518-01 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz to 2.95 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.

The AD9518-0 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.

The AD9518-0 features six LVPECL outputs (in three pairs). The LVPECL outputs operate to 1.6 GHz.

For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available.

In addition, the AD9516 and AD9517 are similar to the AD9518 but have a different combination of outputs.

Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32.

The AD9518-0 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).

The AD9518-0 is specified for operation over the industrial range of −40°C to +85°C.

Applications

Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation

1 AD9518 is used throughout the data sheet to refer to all the members of the AD9518 family. However, when AD9518-0 is used, it refers to that specific member of the AD9518 family.

Features and Benefits

Low phase noise, phase-locked loop (PLL)
For additional information please refer to the data sheet
3 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps

Automatic synchronization of all outputs on power-up
Manual output synchronization available
Available in a 48-lead LFCSP

Data Sheets

Document	note
AD9518-0: 6-Output Clock Generator with Integrated 2.8 GHz VCO Data Sheet (Rev. C)	PDF 1382 kB

Application Notes

Document	note
AN-0974: Multicarrier TD-SCMA Feasibility	PDF 634 kB
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)	PDF 985 kB
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)	PDF 227 kB
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)	PDF 291.7 K
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)	PDF 0
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)	PDF 221 kB
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)	PDF 313 kB
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)	PDF 115 kB
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)	PDF 170 kB
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)	PDF 207 kB
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)	PDF 1679 kB

User Guides

Document	note
UG-075: AD9516-x, AD9517-x, and AD9518-x Evaluation Board User Guide	PDF 1089 kB

Frequently Asked Questions

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Order Information

Part Number	Package	Packing Qty	Temp Range	Price 100-499	Price 1000+	RoHS
AD9518-0ABCPZ Production	48 ld LFCSP (7x7x.85 w/5.5mm EP)	OTH 260	-40 to 85C	6.73	5.72	Y
AD9518-0ABCPZ-RL7 Production	48 ld LFCSP (7x7x.85 w/5.5mm EP)	REEL 750	-40 to 85C	0	5.72	Y
AD9518-0BCPZ Obsolete	48 ld LFCSP 7x7mm (5.1EP)	OTH 260		0	0	Y
AD9518-0BCPZ-REEL7 Obsolete	48 ld LFCSP 7x7mm (5.1EP)	REEL 750		0	0	Y