AD9520-5 12 LVPECL/24 CMOS Output Clock Generator _ BDTIC a Leading Distributor in China

AD9520-5 12 LVPECL/24 CMOS Output Clock Generator

The AD9520-51 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO.

The AD9520 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.

The AD9520 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs.

Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set.

The AD9520 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V.

The AD9520 is specified for operation over the standard industrial range of −40°C to +85°C.

1The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-5 is used, it is referring to that specific member of the AD9520 family.

Applications

Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures

Data Sheet, Rev. 0, 10/08

Features and Benefits

Low phase noise, phase-locked loop (PLL)

Supports external 3.3V/5V VCO/VCXO to 2.4 GHz

1 differential or 2 single-ended reference inputs

Accepts CMOS, LVDS, or LVPECL references to 250 MHz

Accepts 16.67 MHz to 33.3 MHz crystal for reference input

Optional reference clock doubler

Reference monitoring capability

See Data Sheet for Additional Information

Data Sheets

Document	note
AD9520-5: 12 LVPECL/24 CMOS Output Clock Generator Data Sheet (Rev. A)	PDF 240 kB

Application Notes

Document	note
AN-0983: Introduction to Zero-Delay Clock Timing Techniques	PDF 162 kB

User Guides

Document	note

Frequently Asked Questions

Document	note

Order Information

Part Number	Package	Packing Qty	Temp Range	Price 100-499	Price 1000+	RoHS
AD9520-5BCPZ Production	64 ld LFCSP (9x9mm, 6.20mm exposed pad)	OTH 260	-40 to 85C	13.53	11.5	Y
AD9520-5BCPZ-REEL7 Production	64 ld LFCSP (9x9mm, 6.20mm exposed pad)	REEL 750	-40 to 85C	13.53	11.5	Y