AD9523-1 Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs

The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 GHz to 3.1 GHz. Applications

The AD9523-1 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.

The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free, coarse timing adjustment in increments that are equal to half the period of the signal coming out of the VCO.

An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.

Features and Benefits
  • Output frequency: <1 MHz to 1 GHz
  • Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy)
  • Zero delay operation
    Input-to-output edge timing: <150 ps
  • Dual VCO dividers
  • 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
  • 14 dedicated output dividers with jitter-free adjustable delay
  • Adjustable delay: 63 resolution steps of ½ period of VCO output divider
  • Output-to-output skew: <50 ps
  • Duty cycle correction for odd divider settings
  • Automatic synchronization of all outputs on power-up
  • Absolute output jitter: <150 fs at 122.88 MHz Integration range: 12 kHz to 20 MHz
  • See data sheet for additional features
Clock & Timing
RF & Microwave
AD9523/AD9523-1 IBIS Model
Data Sheets
Documentnote
AD9523-1: Low Jitter Clock Generator with14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs (Rev. C)PDF 821 kB
Application Notes
Documentnote
AN-1066: Power Supply Considerations for AD9523, AD9524, and AD9523-1 Low Noise Clocks (Rev. 0)PDF 330 kB
User Guides
Documentnote
UG-182: Evaluation Board User Guide for AD9523-1 Clock GeneratorPDF 711 kB
Order Information
Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
AD9523-1BCPZ Production72 ld LFCSP (10x10mm, 6.0mm exposed pad) OTH 168-40 to 85C10.28.67Y
AD9523-1BCPZ-REEL7 Production72 ld LFCSP (10x10mm, 6.0mm exposed pad) REEL 400-40 to 85C08.67Y
Evaluation Boards
Part NumberDescriptionPriceRoHS
AD9523-1/PCBZEvaluation Board190Y
AD-FMCDAQ2-EBZAD-FMCDAQ2-EBZ Wideband RF data acquisition and signal synthesis module1495Y
Reference Materials
AD9523-1: Low Jitter Clock Generator with14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs (Rev. C) ad9523-1
AD9523-1:低抖动时钟发生器,14路LVPECL/LVDS/HSTL输出或29路LVCMOS输出 数据手册 (Rev. A) ad9523-1
AD9523/AD9523-1 (All Models/All Speed Grades) ad9523
AD9523参考代码 ad9523
AN-1066: Power Supply Considerations for AD9523, AD9524, and AD9523-1 Low Noise Clocks (Rev. 0) ad9523
AN-1066: 低噪声时钟AD9523、AD9524和AD9523-1的电源考虑 (Rev. 0) ad9523
UG-182: Evaluation Board User Guide for AD9523-1 Clock Generator ad9523-1
RF Source Booklet adf9010